Patents by Inventor You-Hua Chou

You-Hua Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651111
    Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Hua Chou, Yi-Jen Lai, Chun-Jen Chen, Perre Kao
  • Publication number: 20200098613
    Abstract: A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided.
    Type: Application
    Filed: November 7, 2019
    Publication date: March 26, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Hua Chou, Chih-Wei Huang, Kuo-Sheng Chuang, Cheng-Chung Chien
  • Publication number: 20200089099
    Abstract: A photomask includes a patterned photomask plate and a supporting member. The patterned photomask plate has a pattern region and a peripheral region surrounding the pattern region. The patterned photomask plate includes a plurality of openings in the pattern region. The supporting member directly abuts the patterned photomask plate and is in a peripheral region of the patterned photomask plate. The supporting member is formed from a different material than the patterned photomask plate.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 19, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Hua CHOU, Kuo-Sheng CHUANG
  • Publication number: 20200091083
    Abstract: A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 19, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Hua CHOU, Kuo-Sheng CHUANG
  • Publication number: 20200058495
    Abstract: A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen HO, You-Hua CHOU, Yen-Hao LIAO, Che-Lun CHANG, Zhen-Cheng WU
  • Publication number: 20200006150
    Abstract: A method including forming a first insulating film over a first fin structure. The method further includes removing the first insulating film to expose a portion of the first fin structure. The method further includes forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.
    Type: Application
    Filed: May 20, 2019
    Publication date: January 2, 2020
    Inventors: Kuo-Sheng CHUANG, You-Hua CHOU, Yusuke ONIKI
  • Patent number: 10510572
    Abstract: A semiconductor processing station including a platform, a load port, and a carrier transport track is provided. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover, and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. The carrier transport track has a bottom side configured to open the load chamber.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Hua Chou, Chih-Wei Huang, Kuo-Sheng Chuang, Cheng-Chung Chien
  • Patent number: 10504778
    Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou, Chia-Lin Hsu
  • Publication number: 20190358823
    Abstract: A method of aligning a substrate contact material to a substrate material includes determining a hardness of a substrate material. The method further includes matching a hardness of a substrate contact material to the hardness of the substrate material. The method further includes adding the substrate contact material to a plurality of contact structures of a substrate handling device, wherein the substrate handling device comprises an edge and a planar surface, a first contact structure of the plurality of contact structures extends from the edge, and a second contact structure of the plurality of contact structures extends from the planar surface.
    Type: Application
    Filed: August 7, 2019
    Publication date: November 28, 2019
    Inventors: You-Hua CHOU, Kuo-Sheng CHUANG
  • Patent number: 10488749
    Abstract: A method for forming a photomask includes the following steps. A substrate is provided, which has a pattern region and a peripheral region surrounding the pattern region. A first etching operation is performed on a first surface of the substrate to remove first portions of the substrate in the pattern region, so as to form recesses in the pattern region of the substrate. A blasting operation is performed on the first surface of the substrate. A BARC layer is formed filling the recesses and over the first surface of the substrate. A second etching operation is performed on a second surface of the substrate opposite to the first surface until portions of the BARC layer in the recesses are exposed. The BARC layer is removed after the second etching operation, so as to form openings in the substrate in the pattern region.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Patent number: 10483115
    Abstract: A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Publication number: 20190337116
    Abstract: A method of using a polishing system includes securing a wafer to a support, wherein the wafer has a first diameter. The method further includes polishing the wafer using a first polishing pad rotating about a first axis, wherein the first polishing pad has a second diameter greater than the first diameter. The method further includes rotating the support about a second axis perpendicular to the first axis after polishing the wafer using the first polishing pad. The method further includes polishing the wafer using a second polishing pad after rotating the support, wherein the second polishing pad has a third diameter less than the first diameter. The method further includes releasing the wafer from the support following polishing the wafer using the second polishing pad.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Inventors: Shih-Chi LIN, Kun-Tai WU, You-Hua CHOU, Chih-Tsung LEE, Min Hao HONG, Chih-Jen WU, Chen-Ming HUANG, Soon-Kang HUANG, Chin-Hsiang CHANG, Chih-Yuan YANG
  • Publication number: 20190311930
    Abstract: A semiconductor processing station including a platform, a load port, and a carrier transport track is provided. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover, and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. The carrier transport track has a bottom side configured to open the load chamber.
    Type: Application
    Filed: June 24, 2019
    Publication date: October 10, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Hua Chou, Chih-Wei Huang, Kuo-Sheng Chuang, Cheng-Chung Chien
  • Patent number: 10399231
    Abstract: A substrate handling device includes a substrate reception area defined by an edge. The substrate reception area includes a planar surface and a plurality of contact structures. At least one contact structure of the plurality of contact structures is located at the edge and at least one contact structure of the plurality of contact structures is located on the planar surface. The substrate reception area and planar surface are made of a first material. Each contact structure of the plurality of contact structures includes a second material different from the first material, the second material having a hardness aligned to a hardness of a substrate material.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Publication number: 20190267458
    Abstract: A transistor includes a channel region, a gate stack, and source and drain structures. The channel region comprises silicon germanium and has a first silicon-to-germanium ratio. The gate stack is over the channel region and comprises a silicon germanium oxide layer over the channel region, a high-? dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-? dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio. The second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio. The channel region is between the source and drain structures.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Sheng CHUANG, You-Hua CHOU, Ming-Chi HUANG
  • Publication number: 20190252248
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Yu-Hung Lin, You-Hua Chou, Sheng-Hsuan Lin, Chih-Wei Chang
  • Publication number: 20190252528
    Abstract: A method and structure for forming a fin bottom diode includes providing a substrate having a plurality of fins extending therefrom. Each of the plurality of fins includes a substrate portion and an epitaxial layer portion over the substrate portion. A first dopant layer is formed on sidewalls of a first region of the substrate portion of each of the plurality of fins. After forming the first dopant layer, a first annealing process is performed to form a first diode region within the first region of the substrate portion. A second dopant layer is formed on sidewalls of a second region of the substrate portion of each of the plurality of fins. After forming the second dopant layer, a second annealing process is performed to form a second diode region within the second region of the substrate portion of each of the plurality of fins.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventor: You-Hua CHOU
  • Patent number: 10357867
    Abstract: A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chi Lin, Kun-Tai Wu, You-Hua Chou, Chih-Tsung Lee, Min Hao Hong, Chih-Jen Wu, Chen-Ming Huang, Soon-Kang Huang, Chin-Hsiang Chang, Chih-Yuan Yang
  • Patent number: 10332769
    Abstract: A semiconductor processing station comprises a platform and a load port, wherein the platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and is configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. A semiconductor process and a method of operating a semiconductor processing station are also provided.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Hua Chou, Chih-Wei Huang, Kuo-Sheng Chuang, Cheng-Chung Chien
  • Publication number: 20190172735
    Abstract: A method includes delivering a wafer into a process chamber, applying a thermal energy to the wafer by a heat source, and moving the heat source substantially along a longitudinal direction of the heat source with respect to the wafer. An apparatus that performs the method is also disclosed.
    Type: Application
    Filed: February 1, 2019
    Publication date: June 6, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Hua CHOU, Min-Hao HONG, Kuan-Chung CHEN