Abstract: A polishing system includes a wafer support that holds a wafer, the wafer having a first diameter. The polishing system further includes a first polishing pad that polishes a first region of the wafer, the first polishing pad having a second diameter greater than the first diameter. The polishing system further includes an auxiliary polishing system comprising at least one second polishing pad that polishes a second region of the wafer, wherein the second polishing pad has a third diameter less than the first diameter, and the wafer support is configured to support the wafer during use of the first polishing pad and the auxiliary polishing system.

Abstract: A semiconductor processing station comprises a platform and a load port, wherein the platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and is configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. A semiconductor process and a method of operating a semiconductor processing station are also provided.

Abstract: A method includes delivering a wafer into a process chamber, applying a thermal energy to the wafer by a heat source, and moving the heat source substantially along a longitudinal direction of the heat source with respect to the wafer. An apparatus that performs the method is also disclosed.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film over a first fin structure and a second insulating film over a second fin structure, coating a protective layer over the second insulating film, removing the first insulating film to expose a portion of the first fin structure, and forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.

Abstract: A semiconductor device has a semiconductor substrate. A silicon germanium layer is disposed on the semiconductor substrate. The silicon germanium layer has a first silicon-to-germanium ratio. A first gate structure is disposed on the silicon germanium layer, and the first gate structure includes an interfacial layer on the silicon germanium layer. The interface layer has a second silicon-to-germanium ratio substantially the same as the first silicon-to-germanium ratio of the silicon germanium layer. The first gate structure also includes a high-dielectric layer on the interfacial layer and a first gate electrode on the high-? dielectric layer.

Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

Abstract: A method and structure for forming a fin bottom diode includes providing a substrate having a plurality of fins extending therefrom. Each of the plurality of fins includes a substrate portion and an epitaxial layer portion over the substrate portion. A first dopant layer is formed on sidewalls of a first region of the substrate portion of each of the plurality of fins. After forming the first dopant layer, a first annealing process is performed to form a first diode region within the first region of the substrate portion. A second dopant layer is formed on sidewalls of a second region of the substrate portion of each of the plurality of fins. After forming the second dopant layer, a second annealing process is performed to form a second diode region within the second region of the substrate portion of each of the plurality of fins.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.

Abstract: Embodiments of the present disclosure include contact structures and methods of forming the same. An embodiment is a method of forming a semiconductor device, the method including forming a contact region over a substrate, forming a dielectric layer over the contact region and the substrate, and forming an opening through the dielectric layer to expose a portion of the contact region. The method further includes forming a metal-silicide layer on the exposed portion of the contact region and along sidewalls of the opening; and filling the opening with a conductive material to form a conductive plug in the dielectric layer, the conductive plug being electrically coupled to the contact region.

Abstract: An embodiment contact plug includes a bilayer structure and a diffusion barrier layer on a sidewall and a bottom surface of the bilayer structure. The bilayer structure includes a conductive core and a conductive liner on a sidewall and a bottom surface of the conductive core. In the embodiment contact plug, the conductive liner comprises cobalt or ruthenium.

Abstract: A method of evaluating characteristics of a work piece includes forming a photosensitive layer on the work piece. Then an ion implantation is performed on the work piece. The work piece is radiated, and an optical intensity of the photosensitive material on the work piece is calculated. The ion implantation pattern is evaluated according to the optical intensity. A chemical structure of the photosensitive material is changed upon the ion implantation. The work piece is recovered by reversing the chemical structure of the photosensitive material or removing the ion interrupted photosensitive material by chemicals.

Abstract: An apparatus for processing a wafer includes a process chamber, a wafer support, a heat source, and a movable device. The wafer support is in the process chamber. The heat source is in the process chamber. The movable device contacts the heat source, in which the movable device is movable with respect to the wafer support.

Abstract: A thin film deposition system and method provide for multiple target assemblies that may be separately powered. Each target assembly includes a target and associated magnet or set of magnets. The disclosure provides a tunable film profile produced by multiple power sources that separately power the target arrangements. The relative amounts of power supplied to the target arrangements may be customized to provide a desired film and may be varied in time to produce a film with varied characteristics.

Abstract: A method of evaluating characteristics of a work piece includes forming a photosensitive layer on the work piece. Then an ion implantation is performed on the work piece. The work piece is radiated, and an optical intensity of the photosensitive material on the work piece is calculated. The ion implantation pattern is evaluated according to the optical intensity. A chemical structure of the photosensitive material is changed upon the ion implantation. The work piece is recovered by reversing the chemical structure of the photosensitive material or removing the ion interrupted photosensitive material by chemicals.

Abstract: A semiconductor device has a semiconductor substrate. A silicon germanium layer is disposed on the semiconductor substrate. The silicon germanium layer has a first silicon-to-germanium ratio. A first gate structure is disposed on the silicon germanium layer, and the first gate structure includes an interfacial layer on the silicon germanium layer. The interface layer has a second silicon-to-germanium ratio substantially the same as the first silicon-to-germanium ratio of the silicon germanium layer. The first gate structure also includes a high-dielectric layer on the interfacial layer and a first gate electrode on the high-? dielectric layer.

Abstract: A substrate handling device includes a substrate reception area defined by an edge. The substrate reception area includes a planar surface and a plurality of contact structures. At least one contact structure of the plurality of contact structures is located at the edge and at least one contact structure of the plurality of contact structures is located on the planar surface. The substrate reception area and planar surface are made of a first material. Each contact structure of the plurality of contact structures includes a second material different from the first material, the second material having a hardness aligned to a hardness of a substrate material.

Abstract: A method of manufacturing a photomask includes depositing a first absorbing layer over a substrate, patterning the first absorbing layer using a photoresist, and depositing a conformal second absorbing layer along surfaces of the first absorbing layer.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film over a first fin structure and a second insulating film over a second fin structure, coating a protective layer over the second insulating film, removing the first insulating film to expose a portion of the first fin structure, and forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.

Abstract: An apparatus for processing a wafer includes a process chamber, a wafer support, a heat source, and a movable device. The wafer support is in the process chamber. The heat source is in the process chamber. The movable device contacts the heat source, in which the movable device is movable with respect to the wafer support.

Abstract: A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.