Patents by Inventor You-Hua Chou

You-Hua Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210341845
    Abstract: A gamma ray generator includes a plate, a plurality of holes and a plurality of gamma ray sources. The plate is configured to rotate along a rotational axis. The holes are disposed in the plate, and the holes are arranged in a matrix. The gamma ray sources are respectively placed in the holes.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Patent number: 11164937
    Abstract: A semiconductor device includes a semiconductor substrate, a capacitor, and an interconnection layer. The capacitor is over the semiconductor substrate and includes a bottom electrode, a top electrode, and an insulator layer. The top electrode has a top surface and a bottom surface rougher than the top surface of the top electrode. The insulator layer is between the bottom electrode and the top electrode. The interconnection layer is over the semiconductor substrate and is electrically connected to the capacitor.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, Chien Lin, You-Hua Chou, Hsing-Yuan Huang, Cheng-Yu Hung
  • Publication number: 20210272799
    Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.
    Type: Application
    Filed: February 27, 2020
    Publication date: September 2, 2021
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Patent number: 11101178
    Abstract: A method including forming a first insulating film over a first fin structure. The method further includes removing the first insulating film to expose a portion of the first fin structure. The method further includes forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Sheng Chuang, You-Hua Chou, Yusuke Oniki
  • Patent number: 11067898
    Abstract: One of gamma ray lithography systems includes a gamma ray generator and a wafer stage. The gamma ray generator is configured to generate a substantially uniform gamma ray. The gamma ray generator includes a plurality of gamma ray sources and a rotational carrier. The rotational carrier is configured to hold the gamma ray sources and rotate along a rotational axis. The wafer stage is disposed below the gamma ray generator and configured to secure a wafer.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Publication number: 20210202241
    Abstract: A structure includes a first dielectric film and a second dielectric film. The second dielectric film is formed on and in contact with the first dielectric film, in which a first pore is formed between the first dielectric film and the second dielectric film, and a thickness of the first dielectric film is smaller than a diameter of the first pore.
    Type: Application
    Filed: March 11, 2021
    Publication date: July 1, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen HO, You-Hua CHOU, Yen-Hao LIAO, Che-Lun CHANG, Zhen-Cheng WU
  • Patent number: 10985058
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Hung Lin, You-Hua Chou, Sheng-Hsuan Lin, Chih-Wei Chang
  • Patent number: 10978329
    Abstract: A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: You-Hua Chou, Chih-Wei Huang, Kuo-Sheng Chuang, Cheng-Chung Chien
  • Patent number: 10950426
    Abstract: A method for manufacturing a dielectric layer includes forming a first dielectric film over a substrate. A first porogen is deposited over the first dielectric film. A second dielectric film is formed on and in contact with the first dielectric film and the first porogen. The first porogen is removed.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, You-Hua Chou, Yen-Hao Liao, Che-Lun Chang, Zhen-Cheng Wu
  • Publication number: 20210050254
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Publication number: 20210035804
    Abstract: A method of patterning a material layer includes the following steps. A first material layer is formed over a substrate, and the first material layer includes a first metal compound. Through a first photomask, portions of the first material layer is exposed with a gamma ray, wherein a first metal ion of the first metal compound in the portions of the first material layer is chemically reduced to a first metal grain. Other portions of the first material layer are removed to form a plurality of first hard mask patterns including the first metal grain.
    Type: Application
    Filed: July 17, 2020
    Publication date: February 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Publication number: 20210033980
    Abstract: One of gamma ray lithography systems includes a gamma ray generator and a wafer stage. The gamma ray generator is configured to generate a substantially uniform gamma ray. The gamma ray generator includes a plurality of gamma ray sources and a rotational carrier. The rotational carrier is configured to hold the gamma ray sources and rotate along a rotational axis. The wafer stage is disposed below the gamma ray generator and configured to secure a wafer.
    Type: Application
    Filed: June 9, 2020
    Publication date: February 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Patent number: 10910483
    Abstract: A method and structure for forming a fin bottom diode includes providing a substrate having a plurality of fins extending therefrom. Each of the plurality of fins includes a substrate portion and an epitaxial layer portion over the substrate portion. A first dopant layer is formed on sidewalls of a first region of the substrate portion of each of the plurality of fins. After forming the first dopant layer, a first annealing process is performed to form a first diode region within the first region of the substrate portion. A second dopant layer is formed on sidewalls of a second region of the substrate portion of each of the plurality of fins. After forming the second dopant layer, a second annealing process is performed to form a second diode region within the second region of the substrate portion of each of the plurality of fins.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: February 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: You-Hua Chou
  • Patent number: 10861721
    Abstract: A method includes delivering a wafer into a process chamber, applying a thermal energy to the wafer by a heat source, and moving the heat source substantially along a longitudinal direction of the heat source with respect to the wafer. An apparatus that performs the method is also disclosed.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: You-Hua Chou, Min-Hao Hong, Kuan-Chung Chen
  • Patent number: 10838295
    Abstract: A method of manufacturing a photomask includes depositing a first absorbing layer over a substrate, patterning the first absorbing layer using a photoresist, and depositing a conformal second absorbing layer along surfaces of the first absorbing layer.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Publication number: 20200357694
    Abstract: A method of forming a conductive powder includes reducing, by a reduction reaction, a conductive powder precursor gas using a plasma to form the conductive powder. The method further includes filtering the conductive powder based on particle size. The method further includes dispersing a portion of the conductive powder having a particle size below a threshold value in a fluid.
    Type: Application
    Filed: July 30, 2020
    Publication date: November 12, 2020
    Inventors: You-Hua CHOU, Kuo-Sheng CHUANG
  • Publication number: 20200350415
    Abstract: A transistor includes a silicon germanium layer, a gate stack, and source and drain features. The silicon germanium layer has a channel region. The silicon germanium layer has a first silicon-to-germanium ratio. The gate stack is disposed over the channel region of the silicon germanium layer and includes a silicon germanium oxide layer over and in contact with the channel region of the silicon germanium layer, a high-? dielectric layer over the silicon germanium oxide layer, and a gate electrode over the high-? dielectric layer. The silicon germanium oxide layer has a second silicon-to-germanium ratio, and the second silicon-to-germanium ratio is substantially the same as the first silicon-to-germanium ratio.
    Type: Application
    Filed: July 11, 2020
    Publication date: November 5, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Sheng CHUANG, You-Hua CHOU, Ming-Chi HUANG
  • Patent number: 10825724
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Patent number: 10763165
    Abstract: A method of forming a conductive powder includes reducing, by a reduction reaction, a conductive powder precursor gas using a plasma. Reducing the conductive powder precursor gas forms the conductive powder. The method further includes filtering the conductive powder based on particle size. The method further includes dispersing a portion of the conductive powder having a particle size below a threshold value in a fluid.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Hua Chou, Kuo-Sheng Chuang
  • Publication number: 20200258814
    Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate. The method includes depositing a first-side UBM layer on a first surface of the semiconductor substrate. The method includes forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the semiconductor substrate. The method includes forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventors: You-Hua CHOU, Yi-Jen LAI, Chun-Jen CHEN, Perre KAO