Patents by Inventor You Liu
You Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230014253Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.Type: ApplicationFiled: August 2, 2021Publication date: January 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Shih-Cheng Chen, Chia-Wei Chang, Chia-Ming Kuo, Tsai-Yu Wen, Yu-Ren Wang
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Patent number: 11557654Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.Type: GrantFiled: October 27, 2021Date of Patent: January 17, 2023Assignee: United Microelectronics Corp.Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
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Publication number: 20220344522Abstract: This invention provides a light-concentrating structure with photosensitivity enhancing effect, including the substrate, buried layer, first electrode layer, second electrode layer, dielectric layer and interconnection structure. The substrate is equipped with a housing space; the buried layer is arranged above the substrate with the housing space; the first electrode layer is arranged above the buried layer; the second electrode layer is arranged in the middle of the first electrode layer; the dielectric layer is arranged above the second electrode layer; the interconnection structure is arranged above the substrate and the first electrode layer surrounding the dielectric layer, which forms an opening and a light-concentrating recess groove.Type: ApplicationFiled: April 21, 2021Publication date: October 27, 2022Inventors: YUAN-TA HSIEH, CHIA-HSIN LEE, HANN-HUEI TSAI, YING-ZONG JUANG, JIAN LI, BO-YOU LIU
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Patent number: 11387781Abstract: A fast start-up crystal oscillator (XO) and a fast start-up method thereof are provided. The fast start-up XO may include a XO core circuit, a frequency synthesizer, and a fast start-up interfacing circuit, wherein the frequency synthesizer may include a voltage control oscillator (VCO) and a divider. The XO core circuit generates a XO signal having a XO frequency. The VCO generates a VCO clock having a VCO frequency, and the divider generates a divided clock having a divided frequency, wherein the VCO frequency is divided by a divisor of the divider to obtain the divided frequency. The fast start-up interfacing circuit transmits the divided clock to the XO core circuit, and then generates a reference clock having the XO frequency according to the XO signal. More particularly, the VCO frequency is calibrated according to the reference clock, in order to make the divided frequency approach the XO frequency.Type: GrantFiled: August 5, 2021Date of Patent: July 12, 2022Assignee: MEDIATEK INC.Inventors: Keng-Meng Chang, Yao-Chi Wang, Yanjie Mo, Sen-You Liu, Chun-Ming Lin
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Publication number: 20220209714Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.Type: ApplicationFiled: March 14, 2022Publication date: June 30, 2022Applicant: MEDIATEK INC.Inventors: Sen-You Liu, Chien-Wei Chen, Keng-Meng Chang, Yao-Chi Wang
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Publication number: 20220157814Abstract: A semiconductor device includes a substrate having a P-type device region and an N-type device region, wherein the P-type device region includes germanium dopants. A first gate oxide layer is formed on the P-type device region and a second gate oxide layer is formed on the N-type device region. The first gate oxide layer and the second gate oxide layer are formed through a same oxidation process. The first gate oxide layer includes nitrogen dopants and the second gate oxide layer does not include the nitrogen dopants.Type: ApplicationFiled: December 22, 2020Publication date: May 19, 2022Inventors: Shi-You Liu, Ming-Shiou Hsieh, Zih-Hsuan Huang, Tsai-Yu Wen, Yu-Ren Wang
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Publication number: 20220140080Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.Type: ApplicationFiled: January 20, 2022Publication date: May 5, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Patent number: 11309835Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.Type: GrantFiled: May 4, 2021Date of Patent: April 19, 2022Assignee: MEDIATEK INC.Inventors: Sen-You Liu, Chien-Wei Chen, Keng-Meng Chang, Yao-Chi Wang
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Publication number: 20220093742Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.Type: ApplicationFiled: October 27, 2021Publication date: March 24, 2022Applicant: United Microelectronics Corp.Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
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Publication number: 20220093741Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.Type: ApplicationFiled: October 27, 2021Publication date: March 24, 2022Applicant: United Microelectronics Corp.Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
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Patent number: 11271078Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.Type: GrantFiled: April 1, 2020Date of Patent: March 8, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Publication number: 20220069773Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.Type: ApplicationFiled: May 4, 2021Publication date: March 3, 2022Inventors: Sen-You Liu, Chien-Wei Chen, Keng-Meng Chang, Yao-Chi Wang
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Patent number: 11195918Abstract: A structure of semiconductor device is provided, including a substrate. A first trench isolation and a second trench isolation are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the germanium doped layer region.Type: GrantFiled: September 18, 2020Date of Patent: December 7, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
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Patent number: 11107689Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.Type: GrantFiled: December 3, 2018Date of Patent: August 31, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ming-Shiou Hsieh, Rong-Sin Lin, Ching-I Li, Neng-Hui Yang
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Patent number: 10796943Abstract: A manufacturing method of a semiconductor structure includes the following steps. A patterned mask layer is formed on a semiconductor substrate. An isolation trench is formed in the semiconductor substrate by removing a part of the semiconductor substrate. A liner layer is conformally formed on an inner sidewall of the isolation trench. An implantation process is performed to the liner layer. The implantation process includes a noble gas implantation process. An isolation structure is at least partially formed in the isolation trench after the implantation process. An etching process is performed to remove the patterned mask layer after forming the isolation structure and expose a top surface of the semiconductor substrate. A part of the liner layer formed on the inner sidewall of the isolation trench is removed by the etching process. The implantation process is configured to modify the etch rate of the liner layer in the etching process.Type: GrantFiled: November 6, 2018Date of Patent: October 6, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Chun-Wei Yu, Yu-Ren Wang, Shi-You Liu, Shao-Hua Hsu
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Patent number: 10773270Abstract: A fluid cleaning apparatus includes a driving assembly including a motor, a gear clutching assembly, a moving assembly, a swaying spray assembly, a sensing assembly, and a controlling module. The fluid cleaning apparatus integrates functions of movement actuation and spraying angle adjustment with the motor and achieves versatile spraying angles for spray-cleaning with apparatus configuration convertible between swaying motion and ceased swaying motion and/or between moving motion and ceased moving motion. Besides, self-propelled movement, spraying pressure modulation, and spraying angle adjustment can be controlled by the control module or manually remotely controlled by a user. Since the fluid cleaning apparatus of the present application saves the conventional installation cost and space needed, as well as resources consumed, for cleaning the bottom of an object to be cleaned, the fluid cleaning apparatus can be extensively applied to multiple fields.Type: GrantFiled: August 29, 2018Date of Patent: September 15, 2020Assignee: National Chung-Shan Institute of Science and TechnologyInventors: Yi-Rong Zeng, Kuan-You Liu, Yu-Ping Wang, Chin-Cheng Wu, Min-Han Chiu, Yew-Shyang Lay
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Publication number: 20200235208Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.Type: ApplicationFiled: April 1, 2020Publication date: July 23, 2020Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Patent number: 10700202Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.Type: GrantFiled: October 28, 2018Date of Patent: June 30, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
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Patent number: 10651275Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.Type: GrantFiled: February 11, 2018Date of Patent: May 12, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Tsai-Yu Wen, Ching-I Li, Ya-Yin Hsiao, Chih-Chiang Wu, Yu-Chun Liu, Ti-Bin Chen, Shao-Ping Chen, Huan-Chi Ma, Chien-Wen Yu
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Publication number: 20200144064Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.Type: ApplicationFiled: December 3, 2018Publication date: May 7, 2020Inventors: Shi-You Liu, Tsai-Yu Wen, Ming-Shiou Hsieh, Rong-Sin Lin, Ching-I Li, Neng-Hui Yang