Patents by Inventor Youn Sung Choi
Youn Sung Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9882051Abstract: Fin Field Effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions are disclosed. In one aspect, a FinFET is provided that includes a substrate and a Fin disposed over the substrate. The Fin includes a source, a drain, and a channel region between the source and drain. A gate is disposed around the channel region. To apply stress to the channel region, a first dielectric material layer is disposed over the substrate and adjacent to one side of the Fin. A second dielectric material layer is disposed over the substrate and adjacent to another side of the Fin. The dielectric material layers apply stress along the Fin, including the channel region. The level of stress applied by the dielectric material layers is not dependent on the volume of each layer.Type: GrantFiled: September 15, 2016Date of Patent: January 30, 2018Assignee: QUALCOMM IncorporatedInventors: Ukjin Roh, Youn Sung Choi, Shashank Ekbote
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Patent number: 9853152Abstract: Fin Field Effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions are disclosed. In one aspect, a FinFET is provided that includes a substrate and a Fin disposed over the substrate. The Fin includes a source, a drain, and a channel region between the source and drain. A gate is disposed around the channel region. To apply stress to the channel region, a first dielectric material layer is disposed over the substrate and adjacent to one side of the Fin. A second dielectric material layer is disposed over the substrate and adjacent to another side of the Fin. The dielectric material layers apply stress along the Fin, including the channel region. The level of stress applied by the dielectric material layers is not dependent on the volume of each layer.Type: GrantFiled: September 15, 2016Date of Patent: December 26, 2017Assignee: QUALCOMM IncorporatedInventors: Ukjin Roh, Youn Sung Choi, Shashank Ekbote
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Patent number: 9634138Abstract: Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate.Type: GrantFiled: August 24, 2016Date of Patent: April 25, 2017Assignee: QUALCOMM IncorporatedInventors: Youn Sung Choi, Ukjin Roh, Shashank Ekbote
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Publication number: 20170084598Abstract: An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Youn Sung Choi, Greg Charles Baldwin
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Patent number: 9543437Abstract: An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.Type: GrantFiled: September 23, 2015Date of Patent: January 10, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Youn Sung Choi, Greg Charles Baldwin
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Publication number: 20160322352Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: ApplicationFiled: July 7, 2016Publication date: November 3, 2016Inventors: Himadri Sekhar PAL, Shashank S. EKBOTE, Youn Sung CHOI
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Patent number: 9412741Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: GrantFiled: October 22, 2015Date of Patent: August 9, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Himadri Sekhar Pal, Shashank S. Ekbote, Youn Sung Choi
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Patent number: 9406769Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.Type: GrantFiled: October 5, 2015Date of Patent: August 2, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shashank S. Ekbote, Kwan-Yong Lim, Ebenezer Eshun, Youn Sung Choi
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Publication number: 20160043076Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: ApplicationFiled: October 22, 2015Publication date: February 11, 2016Inventors: Himadri Sekhar PAL, Shashank S. EKBOTE, Youn Sung CHOI
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Publication number: 20160027888Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Shashank S. EKBOTE, Kwan-Yong LIM, Ebenezer ESHUN, Youn Sung CHOI
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Publication number: 20160013314Abstract: An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.Type: ApplicationFiled: September 23, 2015Publication date: January 14, 2016Inventors: Youn Sung Choi, Greg Charles Baldwin
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Patent number: 9202810Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: GrantFiled: April 3, 2014Date of Patent: December 1, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Himadri Sekhar Pal, Shashank S. Ekbote, Youn Sung Choi
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Patent number: 9202883Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.Type: GrantFiled: June 19, 2015Date of Patent: December 1, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shashank S. Ekbote, Kwan-Yong Lim, Ebenezer Eshun, Youn Sung Choi
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Patent number: 9171901Abstract: An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.Type: GrantFiled: September 5, 2014Date of Patent: October 27, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Youn Sung Choi, Greg Charles Baldwin
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Publication number: 20150287801Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.Type: ApplicationFiled: June 19, 2015Publication date: October 8, 2015Inventors: Shashank S. EKBOTE, Kwan-Yong LIM, Ebenezer ESHUN, Youn Sung CHOI
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Publication number: 20150287717Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: ApplicationFiled: April 3, 2014Publication date: October 8, 2015Inventors: Himadri Sekhar PAL, Shashank S. EKBOTE, Youn Sung CHOI
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Patent number: 9093298Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.Type: GrantFiled: August 22, 2013Date of Patent: July 28, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Shashank S. Ekbote, Kwan-Yong Lim, Ebenezer Eshun, Youn Sung Choi
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Publication number: 20150171217Abstract: An integrated circuit containing finFETs may be formed with fins extending above isolation oxide. A first finFET and a second finFET have exposed fin heights which are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins. In one version, a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform. The fin height is the height of a top of the fin above the substrate. In another version, the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.Type: ApplicationFiled: September 29, 2014Publication date: June 18, 2015Inventors: Ryoung-han KIM, Kwanyong LIM, Youn Sung CHOI
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Patent number: 9029263Abstract: An integrated circuit containing linear structures on regular pitch distances may be formed by forming linear mandrels over a layer of material for the linear structures, with mandrel pitch distances that are twice the desired linear structures' pitch distances. Mandrels for a first plurality of linear structures are shortened. A layer of spacer material is conformally formed over the mandrels and anisotropically etched back to form spacers on lateral surfaces of the mandrels. Spacers on the shortened mandrels are narrower than spacers on the unshortened mandrels as a result of the anisotropic etchback. The mandrels are removed, leaving the spacers in place to form a spacer-based etch mask for the linear structures. The layer of material for the linear structures is etched using the spacer-based etch mask to form the linear structures. The linear structures from the shortened mandrels have lower widths than the linear structures from the unshortened mandrels.Type: GrantFiled: September 29, 2014Date of Patent: May 12, 2015Assignee: Texas Instruments IncorporatedInventors: Ryoung-han Kim, Youn Sung Choi
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Patent number: 8987748Abstract: An integrated circuit containing an MOS transistor with epitaxial source and drain regions may be formed by implanting a retrograde anti-punch-through layer prior to etching the source drain regions for epitaxial replacement. The anti-punch-through layer is disposed between stressor tips of the epitaxial source and drain regions, and does not substantially extend into the epitaxial source and drain regions.Type: GrantFiled: December 19, 2012Date of Patent: March 24, 2015Assignee: Texas Instruments IncorporatedInventors: Himadri Sekhar Pal, Youn Sung Choi, Amitabh Jain