Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract: An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.

Abstract: An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.

Abstract: A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.

Abstract: An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters.

Abstract: An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.

Abstract: An integrated circuit and method of fabricating the same utilizing embedded silicon-germanium (SiGe) source/drain regions, and in which the proximity effect of nearby shallow trench isolation structures is reduced. Embedded SiGe source/drain structures are formed by selective epitaxy into recesses etched into the semiconductor surface, on either side of each gate electrode. The SiGe structures overfill the recesses by at least about 30% of the depth of the recesses, as measured from the interface between the channel region and the overlying gate dielectric at the edge of the gate electrode. This overfill has been observed to reduce proximity effects of nearby shallow trench isolation structures on nearby transistors. Additional reduction in the proximity effect can be obtained by ensuring sufficient spacing between the edge of the gate electrode and a parallel edge of the nearest shallow trench isolation structure.

Abstract: A through-substrate via (TSV) unit cell includes a substrate having a topside semiconductor surface and a bottomside surface, and a TSV which extends the full thickness of the substrate including an electrically conductive filler material surrounded by a dielectric liner that forms an outer edge for the TSV. A circumscribing region of topside semiconductor surface surrounds the outer edge of the TSV. Dielectric isolation is outside the circumscribing region. A tensile contact etch stop layer (t-CESL) is on the dielectric isolation, and on the circumscribing region.

Abstract: A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.

Abstract: An integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.

Abstract: An apparatus includes a plurality of die areas having integrated circuit (IC) die each having circuit elements for performing a circuit function, and scribe line areas between the die areas. At least one test module is formed in the scribe line areas. The test module includes a reference layout that includes at least one active reference MOS transistor that has a reference spacing value for each of a plurality of context dependent effect parameters, and a plurality of variant layouts. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing values for at least one of the plurality of context dependent effect parameters.

Abstract: An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.