Patents by Inventor Youn Sung Choi
Youn Sung Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11444201Abstract: Certain aspects of the present disclosure generally relate to techniques for reducing leakage current in polysilicon-on-active-edge structures. An example transistor structure includes one or more active devices and at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices.Type: GrantFiled: March 26, 2020Date of Patent: September 13, 2022Assignee: QUALCOMM IncorporatedInventors: Youn Sung Choi, Kwanyong Lim, Youseok Suh, Hyunwoo Park
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Publication number: 20220216328Abstract: Certain aspects of the present disclosure generally relate to a self-aligned contact with gate-to-contact short prevention in a multi-gate transistor structure, such as a multi-gate fin field-effect transistor (finFET) structure. An example multi-gate transistor structure includes a semiconductor fin, a first gate, a first spacer, a source or drain contact, and a first nonconductive liner. The first gate is disposed above and partially surrounds a portion of the semiconductor fin. The first spacer is located adjacent to a side of the first gate. The source or drain contact is coupled to a source or drain region of the semiconductor fin. The first nonconductive liner is disposed between the source or drain contact and the first spacer.Type: ApplicationFiled: January 4, 2021Publication date: July 7, 2022Inventors: Youseok SUH, Hyunwoo PARK, Youn Sung CHOI, Kwanyong LIM
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Publication number: 20210305429Abstract: Certain aspects of the present disclosure generally relate to techniques for reducing leakage current in polysilicon-on-active-edge structures. An example transistor structure includes one or more active devices and at least one dummy device disposed at an edge of the transistor structure, wherein the at least one dummy device has a different gate structure than the one or more active devices.Type: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Inventors: Youn Sung CHOI, Kwanyong LIM, Youseok SUH, Hyunwoo PARK
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Patent number: 11075206Abstract: Certain aspects of the present disclosure provide a structure for source or drain in a fin field-effect transistors (finFET) to increase a breakdown voltage between adjacent finFETs in a semiconductor device. One example semiconductor device generally includes a plurality of finFETs, each of the finFETs comprising a source and a drain, wherein at least the source or the drain in at least one finFET of the plurality of finFETs has a profile with at least one rounded tip to increase a breakdown voltage between the at least one finFET and an adjacent finFET in the plurality of finFETs.Type: GrantFiled: December 14, 2018Date of Patent: July 27, 2021Assignee: Qualcomm IncorporatedInventors: Kwanyong Lim, Youn Sung Choi, Ukjin Roh
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Publication number: 20210143153Abstract: Fin Field-Effect Transistor (FET) (FinFET) circuits employing a replacement N-type FET (NFET) source/drains (S/D) are disclosed. The disclosed method for forming a FinFET circuit includes forming two P-type epitaxial S/Ds (epi-S/Ds), one on the fin in the P-type diffusion region and one on the fin in the N-type diffusion region, forming a boundary layer to isolate the P-type epi-S/Ds, and then replacing the P-type epi-S/D under the boundary layer in the N-type diffusion region with an N-type epi-S/D. A mask is employed in steps for replacing the P-type epi-S/D with an N-type epi-S/D in the disclosed method but differs from the mask in the previous method such that vulnerability to variations thereof is reduced. The mask in the disclosed method has a larger acceptable range of variation within which no defects are created, so the disclosed method is less vulnerable to process variation and prevents short defects.Type: ApplicationFiled: November 13, 2019Publication date: May 13, 2021Inventors: Kwanyong Lim, Hyunwoo Park, Youn Sung Choi, Youseok Suh
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Patent number: 10996261Abstract: Aspects generally relate methods and apparatuses of gate leakage detection of a transistor. A gate pad is coupled to a gate of a MOS transistor. A gate leakage detection circuit is coupled to the gate pad, wherein the gate leakage detection circuit is configured to estimate a gate leakage current. Based on the estimated gate leakage current determining a quality of a gate fabrication process.Type: GrantFiled: November 12, 2018Date of Patent: May 4, 2021Assignee: QUALCOMM IncorporatedInventors: Hyunwoo Park, Youn Sung Choi, Stanley Seungchul Song
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Patent number: 10950488Abstract: An integrated circuit containing finFETs may be formed with fins extending above isolation oxide. A first finFET and a second finFET have exposed fin heights which are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins. In one version, a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform. The fin height is the height of a top of the fin above the substrate. In another version, the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.Type: GrantFiled: May 16, 2019Date of Patent: March 16, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ryoung-han Kim, Kwanyong Lim, Youn Sung Choi
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Publication number: 20200256915Abstract: An on-chip test structure has an NMOS transistor (N-type metal oxide semiconductor transistor). The NMOS transistor includes a first source/drain contact and a first gate contact formed in an N-type source/drain opening. The on-chip test structure also has a PMOS transistor (P-type metal oxide semiconductor transistor) adjacent to the NMOS transistor. The PMOS transistor includes a second source/drain contact and a second gate contact formed in a P-type source/drain opening. A distance between the N-type source/drain opening and the P-type source/drain opening is offset relative to a distance between other N-type source/drain openings and P-type source/drain openings, outside the on-chip test structure, that are configured according to a standard technology specification.Type: ApplicationFiled: February 12, 2019Publication date: August 13, 2020Inventors: Youn Sung CHOI, Fadoua CHAFIK, Kwanyong LIM
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Publication number: 20200194440Abstract: Certain aspects of the present disclosure provide a structure for source or drain in a fin field-effect transistors (finFET) to increase a breakdown voltage between adjacent finFETs in a semiconductor device. One example semiconductor device generally includes a plurality of finFETs, each of the finFETs comprising a source and a drain, wherein at least the source or the drain in at least one finFET of the plurality of finFETs has a profile with at least one rounded tip to increase a breakdown voltage between the at least one finFET and an adjacent finFET in the plurality of finFETs.Type: ApplicationFiled: December 14, 2018Publication date: June 18, 2020Inventors: Kwanyong LIM, Youn Sung CHOI, Ukjin ROH
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Patent number: 10600774Abstract: An integrated circuit (IC) is fabricated with transistors and gated diodes having selected epitaxial growth. The transistors may be Field-Effect Transistors (FETs) for example, and more specifically, may be fin-based FETs (finFETs) where fins are fabricated, in part, using an epitaxial growth process. The IC is further fabricated with gated diodes. Selected gated diodes within the IC are fabricated using the epitaxial growth process on the fins of the gated diode to form an anode and a cathode. Other selected gated diodes are fabricated without using epitaxial growth processes to form the anode and the cathode. In still another aspect, selected gated diodes are fabricated with epitaxial growth processes on either the anode or the cathode, but not both. In an exemplary aspect, the other selected gated diodes are part of electrostatic discharge (ESD) protection circuits in an input/output (I/O) region of the IC.Type: GrantFiled: April 6, 2018Date of Patent: March 24, 2020Assignee: QUALCOMM IncorporatedInventors: Youn Sung Choi, Youseok Suh, Kwanyong Lim
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Publication number: 20200049757Abstract: Aspects generally relate methods and apparatuses of gate leakage detection of a transistor. A gate pad is coupled to a gate of a MOS transistor. A gate leakage detection circuit is coupled to the gate pad, wherein the gate leakage detection circuit is configured to estimate a gate leakage current. Based on the estimated gate leakage current determining a quality of a gate fabrication process.Type: ApplicationFiled: November 12, 2018Publication date: February 13, 2020Inventors: Hyunwoo PARK, Youn Sung CHOI, Stanley Seungchul SONG
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Patent number: 10490558Abstract: Aspects for reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells are disclosed herein. An exemplary SRAM strap cell includes a P-type doped well (Pwell) tap electrically coupled to a first supply rail to distribute a first supply voltage to a Pwell region of corresponding SRAM bit cell rows. The SRAM strap cell also includes an N-type doped well (Nwell) tap electrically coupled to a second supply rail to distribute a second supply voltage to an Nwell region of corresponding SRAM bit cell rows. In one exemplary aspect, the Nwell tap can include multiple supply contacts used to couple the second supply rail to the SRAM strap cell to reduce mechanical stress in the Nwell tap. In another exemplary aspect, the Pwell tap can include non-active gates disposed across multiple Fins to stabilize the Fins and reduce or avoid mechanical stress in the Pwell tap.Type: GrantFiled: May 31, 2017Date of Patent: November 26, 2019Assignee: QUALCOMM IncorporatedInventors: Youn Sung Choi, Samit Sengupta, Shashank Ekbote
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Publication number: 20190312025Abstract: An integrated circuit (IC) is fabricated with transistors and gated diodes having selected epitaxial growth. The transistors may be Field-Effect Transistors (FETs) for example, and more specifically, may be fin-based FETs (finFETs) where fins are fabricated, in part, using an epitaxial growth process. The IC is further fabricated with gated diodes. Selected gated diodes within the IC are fabricated using the epitaxial growth process on the fins of the gated diode to form an anode and a cathode. Other selected gated diodes are fabricated without using epitaxial growth processes to form the anode and the cathode. In still another aspect, selected gated diodes are fabricated with epitaxial growth processes on either the anode or the cathode, but not both. In an exemplary aspect, the other selected gated diodes are part of electrostatic discharge (ESD) protection circuits in an input/output (I/O) region of the IC.Type: ApplicationFiled: April 6, 2018Publication date: October 10, 2019Inventors: Youn Sung Choi, Youseok Suh, Kwanyong Lim
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Publication number: 20190273013Abstract: An integrated circuit containing finFETs may be formed with fins extending above isolation oxide. A first finFET and a second finFET have exposed fin heights which are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins. In one version, a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform. The fin height is the height of a top of the fin above the substrate. In another version, the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.Type: ApplicationFiled: May 16, 2019Publication date: September 5, 2019Inventors: Ryoung-han KIM, Kwanyong LIM, Youn Sung CHOI
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Publication number: 20180350819Abstract: Aspects for reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells are disclosed herein. An exemplary SRAM strap cell includes a P-type doped well (Pwell) tap electrically coupled to a first supply rail to distribute a first supply voltage to a Pwell region of corresponding SRAM bit cell rows. The SRAM strap cell also includes an N-type doped well (Nwell) tap electrically coupled to a second supply rail to distribute a second supply voltage to an Nwell region of corresponding SRAM bit cell rows. In one exemplary aspect, the Nwell tap can include multiple supply contacts used to couple the second supply rail to the SRAM strap cell to reduce mechanical stress in the Nwell tap. In another exemplary aspect, the Pwell tap can include non-active gates disposed across multiple Fins to stabilize the Fins and reduce or avoid mechanical stress in the Pwell tap.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Youn Sung Choi, Samit Sengupta, Shashank Ekbote
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Patent number: 10062768Abstract: Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate.Type: GrantFiled: March 9, 2017Date of Patent: August 28, 2018Assignee: QUALCOMM IncorporatedInventors: Youn Sung Choi, Ukjin Roh, Shashank Ekbote
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Patent number: 9953967Abstract: An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.Type: GrantFiled: December 6, 2016Date of Patent: April 24, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Youn Sung Choi, Greg Charles Baldwin
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Publication number: 20180108564Abstract: An integrated circuit containing finFETs may be formed with fins extending above isolation oxide. A first finFET and a second finFET have exposed fin heights which are different by at least 25 percent. The exposed fin height is a vertical height of a sidewall of the fin above the isolation oxide. Gates are formed over the fins. In one version, a fin height of the first finFET is less than a fin height of the second finFET; a thickness of the isolation oxide adjacent to fins of the first finFET and the second finFET is substantially uniform. The fin height is the height of a top of the fin above the substrate. In another version, the isolation oxide is thinner at the first finFET than at the second finFET; the fin heights of the first finFET and the second finFET are substantially equal.Type: ApplicationFiled: December 15, 2017Publication date: April 19, 2018Inventors: Ryoung-han KIM, Kwanyong Lim, Youn Sung Choi
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Patent number: 9922971Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.Type: GrantFiled: July 7, 2016Date of Patent: March 20, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Himadri Sekhar Pal, Shashank S. Ekbote, Youn Sung Choi
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Publication number: 20180061943Abstract: Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate.Type: ApplicationFiled: March 9, 2017Publication date: March 1, 2018Inventors: Youn Sung Choi, Ukjin Roh, Shashank Ekbote