Patents by Inventor Young Hee Kim

Young Hee Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090011552
    Abstract: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.
    Type: Application
    Filed: September 15, 2008
    Publication date: January 8, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri
  • Publication number: 20090008719
    Abstract: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.
    Type: Application
    Filed: September 16, 2008
    Publication date: January 8, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri
  • Publication number: 20080308872
    Abstract: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.
    Type: Application
    Filed: June 14, 2007
    Publication date: December 18, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huiming Bu, Eduard A. Cartier, Bruce B. Doris, Young-Hee Kim, Barry Linder, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen
  • Patent number: 7432567
    Abstract: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: October 7, 2008
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri
  • Publication number: 20080008830
    Abstract: The present invention provides a method for forming a colored oxide film layer on the surface of an article made of iron or a non-iron metal, by subjecting a nickel plating or chrome plating layer formed on the surface of the article to oxidizing heat treatment, in order to impart high corrosion resistance and a variety of vivid colors to the article. The method for forming a colored oxide film layer according to the present invention comprises the steps of: (a) subjecting an article made of iron or a non-iron metal to nickel plating or chrome plating; and (b) subjecting the article thus treated in step (a) to oxidizing heat treatment in an oxidizing atmosphere at 200 to 500° C. for 1 minute to 20 hours, to form a colored oxide film layer on the surface of the plating layer.
    Type: Application
    Filed: January 16, 2007
    Publication date: January 10, 2008
    Inventor: Young Hee Kim
  • Publication number: 20070251605
    Abstract: The present invention provides a method for producing a highly corrosion-resistant colored article made of steel, which are highly corrosion-resistant and has a variety of vivid surface colors, by subjecting the surface of a nitrided steel article to oxidizing heat treatment to form a colored oxide film layer. The method for producing a highly corrosion-resistant colored article made of steel includes the steps of (a) subjecting an article made of steel to nitriding and (b) subjecting the steel article thus treated in step (a) to surface processing such as abrasion, buffing, polishing or the like, and then to oxidizing heat treatment in an oxidizing atmosphere at 100 to 700° C. for 30 seconds to 100 hours, to form a colored oxide film layer on the surface of the steel article.
    Type: Application
    Filed: January 16, 2007
    Publication date: November 1, 2007
    Inventor: Young Hee Kim
  • Publication number: 20070152273
    Abstract: A semiconductor structure and a method of fabricating the same wherein the structure includes at least one nFET device and a least one pFET device, where at least one of the devices is a thinned Si-containing gated device and the other device is a metal gated device are provided. That is, a semiconductor structure is provided wherein at least one of the nFET or pFET devices includes a gate electrode stack comprising a thinned Si-containing electrode, i.e., polysilicon electrode, and an overlying first metal, while the other device includes a gate electrode stack that includes at least the first metal gate, without the thinned Si-containing electrode.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Applicant: INTERNATIONAL BUNISESS MACHINES CORPORATION
    Inventors: Alessandro Callegari, Tze-Chiang Chen, Michael Chudzik, Bruce Doris, Young-Hee Kim, Vijay Narayanan, Vamsi Paruchuri, Michelle Steen, Ying Zhang
  • Publication number: 20070152276
    Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Arnold, Glenn Biery, Alessandro Callegari, Tze-Chiang Chen, Michael Chudzik, Bruce Doris, Michael Gribelyuk, Young-Hee Kim, Barry Linder, Vijay Narayanan, Joseph Newbury, Vamsi Paruchuri, Michelle Steen
  • Publication number: 20070148838
    Abstract: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 28, 2007
    Applicant: International Business Machines Corporation
    Inventors: Bruce Doris, Young-Hee Kim, Barry Linder, Vijay Narayanan, Vamsi Paruchuri
  • Patent number: 7215355
    Abstract: In a mobile communication terminal having a camera rotatively connected thereto, an apparatus and a method for controlling an image is provided. A photographic image generated by the camera can be reoriented so that the image appears inversed as a result of sensing a rotational position of the camera relative to the terminal. A position sensing unit detects a rotational position of a camera; a control unit compares the detected position to a default position and reorients the photographic image if the detected position does not correspond to the default position.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: May 8, 2007
    Assignee: LG Electronics Inc.
    Inventor: Young-Hee Kim
  • Patent number: 7202376
    Abstract: The present invention is related to a method of producing polycarbosilane by heating polydimethylsilane at low pressure within the range of 320˜450° C. using zeolite having the Si/Al or Si/B ratio of 1˜200 as catalyst. This invention uses a zeolite with the structure of ZSM-5, ZSM-11, ZSM-12, zeolite X and zeolite Y, which has the Si/Al or Si/B ratio of 1˜200, as catalyst. When polycarbosilane is produced using a specific zeolite as catalyst, Si/Al or Si/B ratio can be adjusted at any proportion, enabling acidity control of catalyst, and therefore the molecular weight of final products can be easily controlled and the product yield can be improved, compared to conventional solid acid catalysts.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: April 10, 2007
    Assignees: DACC Co., Ltd., Korea Institute of Ceramic Engineering & Technology
    Inventors: Hong Sik Park, Dong Won Lim, Kwang Soo Kim, Young Hee Kim, Doh Hyung Riu, Hyung Rae Kim, Dong Geun Shin, Soo Ryong Kim, Kyung Ja Kim, Hyun Kyu Shin, Dae Hyun Cho
  • Publication number: 20070071918
    Abstract: Disclosed is a biodegradable starch bowl prepared by heating and pressurizing a composition for the biodegradable starch bowl comprising unmodified starch of 20˜60 wt. %; pulp fiber powder of 5˜30 wt. %; solvent of 30˜60 wt. %; photo catalyst of 0.1˜2.0 wt. %; preservative of 0.01˜1 wt. %; and releasing agent of 0.5˜5 wt. % to have a desired shape, and a biodegradable film being attached on the inner surface of the bowl. The biodegradable starch bowl according to the present invention has an improved sterilizing property, deodorizing property, preservative property, releasing property, water-resistance and strength.
    Type: Application
    Filed: January 26, 2005
    Publication date: March 29, 2007
    Inventors: Heon Kim, Sung-Arn Lee, Kang-Soo Kim, Jun-Seung An, Young-Hee Kim
  • Patent number: 7196774
    Abstract: A lithography device including a first revolver, a second revolver and a driving device. The first revolver includes a transmittance control filter. The second revolver includes transmittance profile filter. The driving device is capable of rotating the second revolver. The first revolver is for positioning the at least one transmittance control filter in the light path. The second revolver is for positioning the at least one transmittance profile filters in the light path.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: March 27, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoo-Keun Won, Young-Hee Kim, Young-Ho Park
  • Patent number: 7131217
    Abstract: An apparatus for drying semiconductor wafers includes a bath for receiving semiconductor wafers and for holding a fluid, a chamber for providing an area where vapor is flowable over the bath, a supply pipeline for supplying vapor to the chamber, a vapor discharging pipeline for expunging vapor in the chamber, a fluid discharging pipeline for draining fluid in the chamber therefrom, and a protector for maintaining a distance between the semiconductor wafers during a drying process.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: November 7, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Min Kim, Young-hee Kim, Myung-hwan Shin
  • Publication number: 20060237796
    Abstract: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a worfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
    Type: Application
    Filed: April 21, 2005
    Publication date: October 26, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eduard Cartier, Matthew Copel, Bruce Doris, Rajarao Jammy, Young-Hee Kim, Barry Linder, Vijay Narayanan, Vamsi Paruchuri, Keith Wong
  • Patent number: 7008450
    Abstract: Disclosed are a silicon- and magnesium-containing porous hydroxyapatite, and a preparation method thereof which comprises the steps of performing a hydrothermal treatment of a natural coral and performing a solvothermal treatment.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: March 7, 2006
    Assignees: Korea Institute of Ceramic Engineering and Technology, Meta Biomed Co., Ltd.
    Inventors: Soo-Ryong Kim, Young Hee Kim, Yoon Joo Lee, Hae-Jung Kim, Sang-Jin Jung, Hee Song
  • Publication number: 20050250101
    Abstract: The present invention relates to a method for identifying vehicle and oligonucleotide marker used therefor. More particularly, the present invention is directed to a method for identifying vehicle by using oligonucleotide to which phase transfer agent is bound, and oligonucleotide marker used therefor.
    Type: Application
    Filed: October 16, 2003
    Publication date: November 10, 2005
    Inventors: Jun-mo Gil, Young-hee Kim, Han-oh Park, Sang-Joo Lee
  • Publication number: 20050052526
    Abstract: In a mobile communication terminal having a camera rotatively connected thereto, an apparatus and a method for controlling an image is provided. A photographic image generated by the camera can be reoriented so that the image appears inversed as a result of sensing a rotational position of the camera relative to the terminal. A position sensing unit detects a rotational position of a camera; a control unit compares the detected position to a default position and reorients the photographic image if the detected position does not correspond to the default position.
    Type: Application
    Filed: September 7, 2004
    Publication date: March 10, 2005
    Inventor: Young-Hee Kim
  • Publication number: 20050006605
    Abstract: There is provided a lithography device including a first revolver, a second revolver and a driving device. The first revolver includes a transmittance control filter. The second revolver includes transmittance profile filter. The driving device is capable of rotating the second revolver. According to the present invention, it is possible that a wanted transmittance and transmittance profile can be obtained by rotating a revolver, which has a plurality of transmittance control filters or transmittance profile filter. As a result, the present invention has the advantage of being able to revise variations of light intensity by changing illuminating modes and illuminating conditions.
    Type: Application
    Filed: July 9, 2004
    Publication date: January 13, 2005
    Inventors: Yoo-Keun Won, Young-Hee Kim, Young-Ho Park
  • Patent number: RE38537
    Abstract: A self-diagnostic arrangement for a video display apparatus and method effectuating the same is disclosed. The apparatus according to the present invention includes a cable connector, amplifiers and a cathode ray tube and comprises a microprocessor storing information on a display status, for selectively switching signals to generate horizontal and vertical sync signals for displaying a variety of self-diagnostic displays, an on screen display IC for supplying a blanking signal and a video signal correspondingly responsive to information supplied from the microprocessor and a H/V deflection circuit for supplying on screen display video. signals to the CRT. There is also provided a method of self-diagnosis, which comprises the steps of generating internal horizontal and vertical sync.signals sync signals of predetermined frequency levels and displaying self-diagnostic screens representing video component colors and a display status.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: June 22, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Hee Kim