Patents by Inventor Young Hee Kim
Young Hee Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100148273Abstract: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.Type: ApplicationFiled: February 25, 2010Publication date: June 17, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huiming Bu, Eduard A. Cartier, Bruce B. Doris, Young-Hee Kim, Barry Linder, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen
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Patent number: 7709902Abstract: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.Type: GrantFiled: September 16, 2008Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri
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Publication number: 20100094608Abstract: A method of processing a rigid body interaction in a particle-based fluid simulation includes determining a collision direction based on a normal vector of a pair of input particles and confirming whether parent objects of the particles actually collide against each other after the determination, and calculating a perpendicular impulse based on properties of the parent objects when the collision is confirmed. The method further includes calculating a final collision based boundary force by applying a tangential friction force to the calculated perpendicular impulse to apply the final collision based boundary force to the respective particles.Type: ApplicationFiled: June 9, 2009Publication date: April 15, 2010Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seung Taik Oh, Young Hee Kim, Byung Seok Roh, Bon Ki Koo
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Patent number: 7696036Abstract: An NFET containing a first high-k dielectric portion and a PFET containing a second high-k gate dielectric portion are formed on a semiconductor substrate. A gate sidewall nitride is formed on the gate of the NFET, while the sidewalls of the PFET remain free of the gate sidewall nitride. An oxide spacer is formed directly on the sidewalls of a PFET gate stack and on the gate sidewall nitride on the NFET. After high temperature processing, the first and second dielectric portions contain a non-stoichiometric oxygen deficient high-k dielectric material. The semiconductor structure is subjected to an anneal in an oxygen environment, during which oxygen diffuses through the oxide spacer into the second high-k dielectric portion. The PFET comprises a more stoichiometric high-k dielectric material and the NFET comprises a less stoichiometric high-k dielectric material. Threshold voltages of the PFET and the NFET are optimized by the present invention.Type: GrantFiled: June 14, 2007Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Huiming Bu, Eduard A. Cartier, Bruce B. Doris, Young-Hee Kim, Barry Linder, Vijay Narayanan, Vamsi K. Paruchuri, Michelle L. Steen
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Patent number: 7666732Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a method of fabricating a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction.Type: GrantFiled: September 15, 2008Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri
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Publication number: 20100041221Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.Type: ApplicationFiled: August 14, 2009Publication date: February 18, 2010Applicant: International Business Machines CoporationInventors: John C. Arnold, Glenn A. Biery, Alessandro C. Callegari, Tze-Chiang Chen, Michael P. Chudzik, Bruce B. Doris, Michael A. Gribelyuk, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Joseph S. Newbury, Vamsi K. Paruchuri, Michelle L. Steen
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Publication number: 20100038736Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.Type: ApplicationFiled: August 14, 2008Publication date: February 18, 2010Applicant: International Business Machines CorporationInventors: Solomon Assefa, Jack O. Chu, Martin M. Frank, William M. Green, Young-hee Kim, George G. Totir, Joris Van Campenhout, Yurii A. Vlasov, Ying Zhang
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Publication number: 20090318655Abstract: Provided are polycarbosilane and a method of producing the same. The polycarbosilane contains an allyl group, and thus can be cured by UV absorption when not exposed to the air.Type: ApplicationFiled: June 12, 2009Publication date: December 24, 2009Applicant: TOKAI CARBON KOREA CO., LTD.Inventors: Young Hee KIM, Soo Ryong KIM, Woo Teck KWON, Jung Hyun LEE
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Publication number: 20090302399Abstract: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.Type: ApplicationFiled: August 17, 2009Publication date: December 10, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eduard A. Cartier, Matthew W. Copel, Bruce B. Doris, Rajarao Jammy, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri, Keith Kwong Hon Wong
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Patent number: 7598545Abstract: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.Type: GrantFiled: April 21, 2005Date of Patent: October 6, 2009Assignee: International Business Machines CorporationInventors: Eduard A. Cartier, Matthew W. Copel, Bruce B. Doris, Rajarao Jammy, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri, Keith Kwong Hon Wong
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Publication number: 20090213119Abstract: A three-dimensional (3D) remeshing apparatus includes a curved surface geometry module for calculating one or more geometric elements, including a normal and a curvature, based on data of an input mesh, a vertex grouping module for grouping vertices of the mesh into a general group, an edge group, and an apex group using information of the curvature calculated by the curved surface geometry module, and a projection module for searching for one or more tangent planes corresponding to one or more of the vertices grouped by the vertex grouping module, projecting one or more corresponding vertices on each of the tangent planes, and restoring one or more edges of the input mesh.Type: ApplicationFiled: December 16, 2008Publication date: August 27, 2009Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Seung Taik Oh, Man Jai Lee, Bon Ki Koo, Soon Hyoung Pyo, Young Hee Kim, Seung Hyup Shin, Jang Hee Kim, Byung Seok Roh
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Publication number: 20090206413Abstract: A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) are formed by patterning of a gate dielectric layer, a thin silicon layer, and a silicon-germanium alloy layer. After formation of the source/drain regions and gate spacers, silicon germanium alloy portions are removed from gate stacks. A dielectric layer is formed and patterned to cover an NFET gate electrode, while exposing a thin silicon portion for a PFET. Germanium is selectively deposited on semiconductor surfaces including the exposed silicon portion. The dielectric layer is removed and a metal layer is deposited and reacted with underlying semiconductor material to form a metal silicide for a gate electrode of the NFET, while forming a metal silicide-germanide alloy for a gate electrode of the PFET.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, JR., Jack O. Chu, Young-Hee Kim
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Publication number: 20090181505Abstract: In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last process.Type: ApplicationFiled: January 14, 2008Publication date: July 16, 2009Inventors: Takashi Ando, Eduard A. Cartier, Changhwan Choi, Elizabeth A. Duch, Bruce B. Doris, Young-Hee Kim, Vijay Narayanan, James Pan, Vamsi K. Paruchuri
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Publication number: 20090142891Abstract: In one embodiment, the present invention provides a method of manufacturing a semiconducting device that includes providing a silicon containing substrate having PFET device and NFET device, wherein the NFET device includes an amorphous silicon containing region; depositing a tensile strain silicon nitride layer atop the NFET device and the PFET device, wherein the silicon nitride tensile strain layer induces a tensile strain in a channel of the NFET device region; annealing to crystallize the amorphous silicon containing region, wherein the tensile strain silicon nitride layer positioned atop the PFET device confines oxygen within a channel positioned within the silicon containing substrate underlying the PFET device, wherein the oxygen within the channel shifts a threshold voltage of the PFET device towards a valence band of silicon of the silicon containing substrate; and removing the tensile strain silicon nitride layer.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Applicant: International Business Machines CorporationInventors: Young-Hee Kim, Jeffrey W. Sleight, Huiming Bu, Rick Carter, Mike Hargrove
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Publication number: 20090112526Abstract: Provided are a system and method for simulating fluid particles having multi-resolution. In the method, given particle data expressing fluid is analyzed in an fluid particle analyzing module so that data for determining resolutions is obtained. A resolution of each of regions is determined using the obtained data in a resolution level determining module. Particles of each of the regions are reformed to particles corresponding to the resolution of each of the regions using the determined resolution of each of the regions in a fluid particle reforming module. Position data of fluid particles of a next frame is obtained after a simulation using the reformed particles in a multi-resolution fluid simulation module. Therefore, the fluid simulation having the high resolution can be performed in limited computing resources by applying different resolutions to each of the regions.Type: ApplicationFiled: April 11, 2008Publication date: April 30, 2009Applicant: Electronics and Telecommunications Research InstituteInventors: Janghee KIM, Manjai LEE, Bon Ki KOO, Soon Hyoung PYO, Seungtaik OH, Young Hee KIM, Byung Seok ROH
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Publication number: 20090104467Abstract: Disclosed is a surface protective film, a method for fabricating the same, and pouch, and a method for fabricating the same. The surface protective film includes a stack of films including a middle layer, and a first skin layer and a second skin layer on opposite sides of the middle layer, wherein at least one of the first skin layer and the second skin layer is formed of a resin having a hardness lower than a hardness of a surface to be protected by the surface protective film, and the middle layer is formed of a resin including high density polyethylene, thereby permitting protection of a display surface without formation of scratch at a very low cost compared to the related art without aging and with slip.Type: ApplicationFiled: October 20, 2008Publication date: April 23, 2009Inventors: Ki Mock Son, Jong Hak Kim, Young Hee Kim, Han Jun Kang, Hee Sik Han, Sang Min Lee, Jong Seon Kim
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Patent number: 7476622Abstract: A gate is formed on a device formation region of a semiconductor substrate, and source and drain regions are formed in the device formation region of the semiconductor substrate adjacent respective sides of the gate. The gate is formed to include a gate dielectric layer, a gate conductive layer and sidewall spacers located at respective sidewalls of the gate conductive layer. An etch stop layer is formed over the source region, the drain region and the sidewall spacers of the gate to obtain an intermediate structure, and a planarized first interlayer insulating film is formed over a surface of the intermediate structure. The first insulating layer is dry etched until the etch stop layer over the source region, the drain region and the sidewall spacers is exposed to form self-aligned contact holes in the first interlayer insulating over the source region and the drain region, respectively.Type: GrantFiled: November 14, 2003Date of Patent: January 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-joon Cho, Young-hee Kim, Young-hwan Yun, Doo-heun Baek
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Publication number: 20090008720Abstract: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.Type: ApplicationFiled: September 16, 2008Publication date: January 8, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce B. Doris, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri
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Publication number: 20090011552Abstract: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.Type: ApplicationFiled: September 15, 2008Publication date: January 8, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce B. Doris, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri
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Publication number: 20090008719Abstract: A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.Type: ApplicationFiled: September 16, 2008Publication date: January 8, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce B. Doris, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri