Patents by Inventor Young Hee Kim

Young Hee Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130154609
    Abstract: Provided are an apparatus and a method for recoding neuronal signals. The apparatus may include a substrate with an electrode region, a plurality of stimulation electrodes arranged on the electrode region to have a specific arrangement, and at least one recording electrode provided between adjacent ones of the stimulation electrodes and attached with an axon of the neuronal cell. Each of the stimulation electrodes may be attached with a body of a neuronal cell.
    Type: Application
    Filed: September 13, 2012
    Publication date: June 20, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sang Don JUNG, Young Hee KIM, Nam Seob BAEK
  • Publication number: 20130147789
    Abstract: A real-time three-dimensional (3D) real environment reconstruction apparatus and method are provided. The real-time 3D real environment reconstruction apparatus reconstructs a 3D real environment in real-time, or processes data input through RGB-D cameras in real-time using a plurality of GPUs so as to reconstruct a wide ranging 3D real environment.
    Type: Application
    Filed: July 13, 2012
    Publication date: June 13, 2013
    Applicant: Electronics & Telecommunications Research Institute
    Inventor: Young-Hee KIM
  • Publication number: 20130140634
    Abstract: A method of replacing semiconductor material with metal, Replacement Metal Gate Field Effect Transistors (RMG FETs) and Contacts (RMCs), and Integrated Circuit (IC) chips including the FETs and/or RMCs. A patterned semiconductor layer, e.g., silicon, is formed on a dielectric layer, e.g., a layered gate dielectric. A field dielectric layer fills between shapes in the patterned semiconductor layer. Metal is deposited on the shapes. The wafer is annealed to replace semiconductor in each shape with metal to form metal FET gates or contacts.
    Type: Application
    Filed: December 5, 2011
    Publication date: June 6, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Christopher D'Emic, Young-Hee Kim, Dae-gyu Park, Jeng-Bang Yau
  • Publication number: 20130136807
    Abstract: Disclosed herein is an insect proof or insecticidal composition for the conservation of cultural properties against termites, comprising an extract of Asarum sieboldii as an active ingredient. Based on a methanol extract of Asarum sieboldii or a hexane fraction from the methanol extract, the composition is environmentally friendly and non-toxic to humans and animals. Also, because of its excellent insecticidal activity against termites, the composition can be used to protect wooden structures and cultural properties from termite damage, which is a great threat to the life of wooden structures and cultural properties, without toxicity to humans and animals.
    Type: Application
    Filed: April 19, 2012
    Publication date: May 30, 2013
    Applicant: NATIONAL RESEARCH INSTITUTE OF CULTURAL HERITAGE
    Inventors: Chang Wook JO, Young Hee KIM, Jin Young HONG, Mi Hwa JUNG, Soo Ji KIM, Jeung-Min LEE, Jung Eun CHOI, So Young JEONG
  • Publication number: 20130136815
    Abstract: An insect-repellent or insecticidal composition comprising an extract or an organic solvent fraction of oak vinegar as an effective ingredient, is provided. The composition comprising extract or organic solvent fraction of oak vinegar as an effective ingredient has superior insect-repellent or insecticidal activities against lasioderma serricorne, which damages tobacco, grains, paper or clothes, reticulitermes speratus kyushuensis Morimoto, which chews the woods from within, or sitophilus oryzae, which has strong tolerance to insecticides, and therefore, can be applied efficaciously as an insect-repellent or insecticidal composition to conserve wooden furniture, an old house, or many organic cultural heritages.
    Type: Application
    Filed: September 10, 2010
    Publication date: May 30, 2013
    Applicant: Republic of Korea (National Research Institute of Cultural Heritage)
    Inventors: Mi Hwa Jung, Jin Young Hong, Chang Wook Jo, Young-Hee Kim, Jung Eun Choi, So Young Jeong, Soon Hyoung Ghang
  • Publication number: 20130129848
    Abstract: An insect-repellent and insecticidal composition comprising extract or fraction of phellodendron amurense as an active ingredient is provided. The extract of phellodendron amurense, or the hexane (Hex) extract, methylene chloride (MC) fraction, or ethyl acetate (EtOAc) fraction provides insect-repellent or insecticidal activities against lasioderma serricorne which harms tobacco, crops, paper, clothes or wood, or against sitophilus oryzae which has strong tolerance to insecticide, and thus can be effectively applied as an insect-repellent or insecticidal composition to conserve wooden furniture, an old house, or many organic cultural heritages.
    Type: Application
    Filed: September 10, 2010
    Publication date: May 23, 2013
    Inventors: Mi Hwa Jung, Jin Young Hong, Chang Wook Jo, Young-Hee Kim, Jung Eun Choi, So Young Jeong, Soon Hyoung Ghang
  • Patent number: 8445316
    Abstract: A dielectric material layer is formed on a front surface of a photovoltaic device. A patterned PMMA-type-material-including layer is formed on the dielectric material layer, and the pattern is transferred into the top portion of the photovoltaic device to form trenches in which contact structures can be formed. In one embodiment, a blanket PMMA-type-material-including layer is deposited on the dielectric material layer, and is patterned by laser ablation that removes ablated portions of PMMA-type-material. The PMMA-type-material-including layer may also include a dye to enhance absorption of the laser beam. In another embodiment, a blanket PMMA-type-material-including layer may be deposited on the dielectric material layer and mechanically patterned to form channels therein. In yet another embodiment, a patterned PMMA-type-material-including layer is stamped on top of the dielectric material layer.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Jeffrey C. Hedrick, Mahmoud Khojasteh, Young-Hee Kim
  • Patent number: 8383483
    Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: February 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Glenn A. Biery, Alessandro C. Callegari, Tze-Chiang Chen, Michael P. Chudzik, Bruce B. Doris, Michael A. Gribelyuk, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Joseph S. Newbury, Vamsi K. Paruchuri, Michelle L. Steen
  • Publication number: 20130045562
    Abstract: A method of forming a photovoltaic device containing a buried emitter region and vertical metal contacts is provided. The method includes forming a plurality of metal nanoparticles on exposed portions of a single-crystalline silicon substrate that are not covered by patterned antireflective coatings (ARCs). A metal nanoparticle catalyzed etching process is then used to form trenches within the single-crystalline silicon substrate and thereafter the metal nanoparticles are removed from the trenches. An emitter region is then formed within exposed portions of the single-crystalline silicon substrate, and thereafter a metal contact is formed atop the emitter region.
    Type: Application
    Filed: August 18, 2011
    Publication date: February 21, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jun Liu, Qiang Huang, Young-Hee Kim
  • Publication number: 20130032865
    Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
    Type: Application
    Filed: September 7, 2012
    Publication date: February 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
  • Publication number: 20130032883
    Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
  • Publication number: 20130025663
    Abstract: A method for texturing a single-crystalline silicon substrate is provided in which inverted pyramids are formed within the textured single-crystalline silicon substrate. The textured single-crystalline silicon substrates containing the inverted pyramids provided by the present disclosure have a low reflectance associated therewith and thus can be used as a component of a silicon solar cell. The method includes forming a plurality of openings that extend beneath an upper surface of a single-crystalline silicon substrate, and forming inverted pyramids in each of the openings by expanding each opening.
    Type: Application
    Filed: July 27, 2011
    Publication date: January 31, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jun Liu, Qiang Huang, Young-hee Kim
  • Publication number: 20120322200
    Abstract: A dielectric material layer is formed on a front surface of a photovoltaic device. A patterned PMMA-type-material-including layer is formed on the dielectric material layer, and the pattern is transferred into the top portion of the photovoltaic device to form trenches in which contact structures can be formed. In one embodiment, a blanket PMMA-type-material-including layer is deposited on the dielectric material layer, and is patterned by laser ablation that removes ablated portions of PMMA-type-material. The PMMA-type-material-including layer may also include a dye to enhance absorption of the laser beam. In another embodiment, a blanket PMMA-type-material-including layer may be deposited on the dielectric material layer and mechanically patterned to form channels therein. In yet another embodiment, a patterned PMMA-type-material-including layer is stamped on top of the dielectric material layer.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 20, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Jeffrey C. Hedrick, Mahmoud Khojasteh, Young-Hee Kim
  • Patent number: 8335676
    Abstract: A method for calculating a force acting on an interface between immiscible fluids in an SPH (Smoothed Particle Hydrodynamics) based fluid simulation includes: calculating a force caused by viscosities of the fluids; calculating a force caused by pressures of the fluids; calculating an external force applied to the fluids from outside; and calculating an interactive force caused by interaction between the fluids. The force acting on the interface between the immiscible fluids are obtained by using sum of the force caused by the viscosities, the force caused by the pressures, the external force and the interactive force. The interactive force is a surface tensional force calculated based on a pressure acting on the interface between the fluids.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: December 18, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Hee Kim, Bon Ki Koo
  • Publication number: 20120315752
    Abstract: A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.
    Type: Application
    Filed: March 7, 2012
    Publication date: December 13, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byung-Hong CHUNG, Young-Hee KIM, In-Sun YI, Han-Mei CHOI
  • Patent number: 8269771
    Abstract: A three-dimensional (3D) remeshing apparatus includes a curved surface geometry module for calculating one or more geometric elements, including a normal and a curvature, based on data of an input mesh, a vertex grouping module for grouping vertices of the mesh into a general group, an edge group, and an apex group using information of the curvature calculated by the curved surface geometry module, and a projection module for searching for one or more tangent planes corresponding to one or more of the vertices grouped by the vertex grouping module, projecting one or more corresponding vertices on each of the tangent planes, and restoring one or more edges of the input mesh.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: September 18, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Taik Oh, Man Jai Lee, Bon Ki Koo, Soon Hyoung Pyo, Young Hee Kim, Seung Hyup Shin, Jang Hee Kim, Byung Seok Roh
  • Publication number: 20120125916
    Abstract: Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.
    Type: Application
    Filed: February 1, 2012
    Publication date: May 24, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, William M. Green, Young-hee Kim, Joris Van Campenhout, Yurii A. Vlasov
  • Publication number: 20120131592
    Abstract: Disclosed are a parallel computing method for particle based simulation that may decrease a calculation delay due to data communication by simultaneously performing the data communication and a simulation calculation and increasing parallelism of a task, and an apparatus thereof. The parallel computing method for particle based simulation according to an exemplary embodiment to the present invention may include decomposing the whole calculation domain of a manager node into a plurality of sub-domains based on a grid macro-cell based orthogonal recursive bisection (ORB) method; allocating the decomposed sub-domains to worker nodes; and performing load balancing with respect to the worker nodes.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 24, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INTITUTE
    Inventors: Young Hee KIM, Soon Hyoung Pyo, Bon Ki Koo
  • Patent number: 8178382
    Abstract: A vertical stack of a first silicon germanium alloy layer, a second epitaxial silicon layer, a second silicon germanium layer, and a germanium layer are formed epitaxially on a top surface of a first epitaxial silicon layer. The second epitaxial silicon layer, the second silicon germanium layer, and the germanium layer are patterned and encapsulated by a dielectric cap portion, a dielectric spacer, and the first silicon germanium layer. The silicon germanium layer is removed between the first and second silicon layers to form a silicon germanium mesa structure that structurally support an overhanging structure comprising a stack of a silicon portion, a silicon germanium alloy portion, a germanium photodetector, and a dielectric cap portion. The germanium photodetector is suspended by the silicon germanium mesa structure and does not abut a silicon waveguide. Germanium diffusion into the silicon waveguide and defect density in the germanium detector are minimized.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: May 15, 2012
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, Jack O. Chu, Martin M. Frank, William M. Green, Young-hee Kim, George G. Totir, Joris Van Campenhout, Yurri A. Vlasov, Ying Zhang
  • Patent number: 8097500
    Abstract: In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last process.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Eduard A. Cartier, Changhwan Choi, Elizabeth A. Duch, Bruce B. Doris, Young-Hee Kim, Vijay Narayanan, James Pan, Vamsi K. Paruchuri