Abstract: A semiconductor memory device which a pad for receiving a power voltage, a first power line connected to the pad, and a plurality of second power lines respectively connected to memory cells of a repair unit. A selection circuit outputs selection signals for selecting the memory cells of the array in the repair unit in response to a row address in a test operation mode. A power switch circuit operates in response to the selection signals, and connects the second power line connected to the selected memory cells with the first power line in the test operation mode. The power switch circuit disconnects the remaining second power lines from the first power line.

Abstract: An apparatus and method for embedding and extracting a capturing-resistant audio watermark based on discrete wavelet transform, and a copyright management system using the same are provided. The apparatus for embedding a wavelet based audio watermark includes: a framing unit for dividing an input audio signal into small signals with a regular length; a discrete wavelet transform unit for calculating an mean value of wavelet coefficients by transforming the small signals based on a discrete wavelet transform; and an embedding unit for changing the calculated mean value according to a watermark where a synchronization signal is inserted and inserting the watermark into the audio signal.

Abstract: The present invention relates to a network-based robot system and an executing method thereof. According to an exemplary embodiment of the present invention, predefine environment information is expressed in a universal data model (UDM) described by a linkage that shows a relationship among nodes, each node being an object of a virtual space abstracted by a real physical space. The universal data model is updated based on the context information, event occurrence information is transmitted to a task engine when the context information data value is changed, and the task engine executes a corresponding task through reasoning and invokes an external service. The robot can better recognize the context information by utilizing the external sensing function and external processing function. In addition, the robot system can provide an active service by reasoning the recognized context information and obtaining high-level information.

Abstract: Disclosed is a system and method for tracing illegally copied contents on the basis of fingerprint. Purchaser information is inserted into digital contents that include image, audio or video data using a fingerprinting system when the digital contents are sold in the distribution process of the digital contents. If the contents purchaser has illegally copied and distributed the contents through the Internet or a P2P (Peer to Peer) server that is a file sharing server, the corresponding contents are searched for using a searcher and the corresponding purchaser is traced on the basis of fingerprint information inserted into the contents.

Abstract: A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit line comprising a bit line pair.

Abstract: An integrated circuit comprising a memory cell array capable of simultaneously performing data read and write operations is provided. The integrated circuit to which inputs and outputs (IOs) are separately provided and to which a write address and a read address are simultaneously input during one period of a clock signal comprises a plurality of memory blocks, the memory blocks comprising a plurality of sub-memory blocks, a plurality of data memory blocks corresponding to the memory blocks, and a tag memory controlling unit, which writes data to the memory blocks or reads data from the memory blocks in response to the write address or the read address, wherein access to the same sub-memory block is not simultaneously performed when the write address and the read address are the same.

Abstract: A communication method in a network robot system having a middleware processing communication between a plurality of sensors, a server, and a robot, the method including: setting previously a communication framework of the middleware for distributed processing of function of the robot by using the plurality of sensors and the server; and performing a communication between the plurality of sensors, the server and the robot by using the communication framework set previously, wherein one of synchronous and asynchronous operations is performed according to a size of data for a remote object called from the robot.

Abstract: An apparatus for providing a content-information service comprises: a user-content interface for receiving content-provision request information collected by several user I/O interfaces which includes a voice recognition interface, and providing content data corresponding to the provision request information to users; a content-provision relay for requesting the content data using content-associated information corresponding to the content-provision request information, and transmitting the content data to the user-content interface; a content-information manager for registering and managing the content-associated information associated with the content data; and a content-storage unit for storing and managing a plurality of providable content data.

Abstract: Memory devices are provided which are capable of performing burst operations by simultaneously writing/reading a plurality of data bits to/from memory in response to a selection of a single wordline, and which are capable of controlling data input/output for interruption of burst operation interruptions without having to employ complex control circuitry.

Abstract: The present invention relates to a method for blindly embedding and extracting a watermark by using wavelet transform and a human visual system (HVS) model, which obtains both robustness and invisibility by applying the HVS model of NVF or JND imitating a human visual system to a middle frequency band for wavelet transformation and using a quantization step determined adaptively according to the importance of wavelet coefficient.

Abstract: A semiconductor memory device and a method of operating the semiconductor memory device are disclosed. The semiconductor memory device comprises a memory cell array having a plurality of cell array blocks. The cell array blocks are operationally divided into a plurality of memory planes using a memory determining unit. Each of the memory planes comprises at least one cell array block and is capable of executing independent data access operations using an independent operating mode.

Abstract: A column select circuit in a Static Random Access Memory (SRAM) having a three-dimensional layout can include a lower CMOS layer in a substrate and an upper NMOS layer above the lower layer. An intermediate PMOS layer is located between the upper NMOS layer and the lower CMOS layer.

Abstract: A method of controlling an integrated circuit (IC) capable of simultaneously performing a data read operation and a data write operation is provided. The method comprises (a) receiving a write address, a read address, and write data, (b) determining, a memory block and a data memory block in which a data read operation and a data write operation are to be performed in response to the write address and the read address, (c) performing the data read operation or the data write operation in the data memory block according to the determination of step (b), and (d) performing the data read operation or the data write operation in the memory block according to the determination of step (b).

Abstract: Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin-film transistors. These thin-film transistors include a first PMOS thin-film pull-up transistor and a first NMOS thin-film pass transistor. These thin-film transistors are electrically coupled to one of the first pair of bit lines. The first column of memory cells includes a column of TFT SRAM cells.

Abstract: Memory devices are provided which are capable of performing burst operations by simultaneously writing/reading a plurality of data bits to/from memory in response to a selection of a single wordline, and which are capable of controlling data input/output for interruption of burst operation interruptions without having to employ complex control circuitry.

Abstract: A column select circuit in a Static Random Access Memory (SRAM) having a three-dimensional layout can include a lower CMOS layer in a substrate and an upper NMOS layer above the lower layer. An intermediate PMOS layer is located between the upper NMOS layer and the lower CMOS layer.

Abstract: A fingerprint code structure and a collusion customer identifying method using the same are disclosed. The collusion customer identifying method includes the steps of: inserting a fingerprint code including a contents code and a customer code in a contents; extracting the fingerprint code; determining whether there is an collusion attack on the contents by using the extracted fingerprint code; and identifying the collusion customers participating in the collusion attack according to a result of the determination. The collusion customer identifying method can trace collusion customers participating in the collusion attack by using a location of undetectable code although the collusion customers eliminate the fingerprint code from the multimedia contents by participating in the collusion attack.

Abstract: A true bit line can extend across a memory cell area of the memory device in a first direction and a complementary bit line can extend across the memory cell area in a second direction opposing the first direction, wherein the true bit line and the complementary bit line comprising a bit line pair.

Abstract: Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin-film transistors. These thin-film transistors include a first PMOS thin-film pull-up transistor and a first NMOS thin-film pass transistor. These thin-film transistors are electrically coupled to one of the first pair of bit lines. The first column of memory cells includes a column of TFT SRAM cells.

Abstract: A semiconductor memory device and a method of operating the semiconductor memory device are disclosed. The semiconductor memory device comprises a memory cell array having a plurality of cell array blocks. The cell array blocks are operationally divided into a plurality of memory planes using a memory determining unit. Each of the memory planes comprises at least one cell array block and is capable of executing independent data access operations using an independent operating mode.