Abstract: An apparatus and method for embedding and extracting digital watermarks using a blind mode based on wavelet transform which is robust to external attacks while being capable of minimizing a degradation in picture quality caused by embedding of the watermarks. In accordance with the invention, watermarks protection of the copyright for desired data are embedded in DC component domains of wavelet-transformed domains. In accordance with the invention, embedding of watermarks in a target image corresponding to a target domain in which the watermarks are to be embedded, is achieved by generating a data stream of the watermarks in accordance with a key value selected by the user, generating index information representing positions where the watermarks are to be embedded, in accordance with a key value selected by the ser, and reflecting the watermark data stream on data values of pixels in the target image at the positions based on the index information.

Abstract: Disclosed is an amplitude-scaling resilient audio watermarking apparatus and method. An encoding apparatus includes: a polyphase filterbank for dividing an audio signal into a plurality of subbands; a psychoacoustic module for applying a psychoacoustic model to the audio signal to provide a signal-to-mask ratio; a watermark encoder for evaluating an encoding parameter from the subbands according to the signal-to-mask ratio and embedding the encoding parameter and a watermark into subbands corresponding to the middle frequency; and a synthesis filterbank for synthesizing the subband signals to output a watermarked audio signal.

Abstract: An integrated circuit and a method of reading and writing data at the same time are provided. The integrated circuit has separate input and output ports and a write address and a read address are input during a period of a clock signal. The circuit includes memory blocks that respectively include a plurality of sub memory blocks, cache memory blocks that respectively correspond to the memory blocks, and a tag memory control unit. The tag memory control unit controls reading data from and writing data to the memory blocks and the cache memory blocks in response to the write address or the read address. In particular, reads of the data from or writes of the data to the memory block and the cache memory block at the same time are performed if an upper address of the read address and an upper address of the write address are identical to each other.

Abstract: A semiconductor memory device which a pad for receiving a power voltage, a first power line connected to the pad, and a plurality of second power lines respectively connected to memory cells of a repair unit. A selection circuit outputs selection signals for selecting the memory cells of the array in the repair unit in response to a row address in a test operation mode. A power switch circuit operates in response to the selection signals, and connects the second power line connected to the selected memory cells with the first power line in the test operation mode. The power switch circuit disconnects the remaining second power lines from the first power line.

Abstract: An integrated circuit comprising a memory cell array capable of simultaneously performing data read and write operations is provided. The integrated circuit to which inputs and outputs (IOs) are separately provided and to which a write address and a read address are simultaneously input during one period of a clock signal comprises a plurality of memory blocks, the memory blocks comprising a plurality of sub-memory blocks, a plurality of data memory blocks corresponding to the memory blocks, and a tag memory controlling unit, which writes data to the memory blocks or reads data from the memory blocks in response to the write address or the read address, wherein access to the same sub-memory block is not simultaneously performed when the write address and the read address are the same.

Abstract: A method of controlling an integrated circuit (IC) capable of simultaneously performing a data read operation and a data write operation is provided. The method comprises (a) receiving a write address, a read address, and write data, (b) determining, a memory block and a data memory block in which a data read operation and a data write operation are to be performed in response to the write address and the read address, (c) performing the data read operation or the data write operation in the data memory block according to the determination of step (b), and (d) performing the data read operation or the data write operation in the memory block according to the determination of step (b).

Abstract: An integrated circuit and a method of reading and writing data at the same time are provided. The integrated circuit has separate input and output ports and a write address and a read address are input during a period of a clock signal. The circuit includes memory blocks that respectively include a plurality of sub memory blocks, cache memory blocks that respectively correspond to the memory blocks memory blocks, and a tag memory control unit. The tag memory control unit controls reading data from and writing data to the memory blocks and the cache memory blocks in response to the write address or the read address. In particular, reads of the data from or writes of the data to the memory block and the cache memory block at the same time are performed if an upper address of the read address and an upper address of the write address are identical to each other.

Abstract: Methods and apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus. Read and write operations are sequentially performed in a same cycle using QDR2 (Quadruple Data Rate 2) wherein each of the input and output modes operate at a 2-bit burst mode and a double data rate (DDR) mode, thereby minimizing cycle time or read and write operations are sequentially performed in a same cycle using QDR4 (Quadruple Data Rate 4), wherein each of the input and output modes operate at a 4-bit burst mode and a DDR mode, thereby minimizing the cycle time. In another aspect, when a read command is input in one cycle, a read operation is performed in synchronization with a rising edge of clock and a write operation is performed in synchronization with a signal that operates during the read operation.

Abstract: The present invention relates to a protection of copyrights of digital data, and more particularly, to a real-time blind watermarking method using quantization, in which a watermark information for representing ownership is embedded in a digital image, video or the like so as not to be visually or aurally discriminated and is extracted after various attacks such as edit or the like, and which can be used in all compression ways. The real-time video watermarking system is a blind method and is simple. In order to perform DCT with respect to an original frame and enhance the robustness, the watermark is embedded in a low frequency component. Further, since the DCT is not performed with respect to all blocks, the invention has a rapid operation speed regardless of the size of the video frame.

Abstract: A semiconductor memory device having redundancy with no performance penalty. The semiconductor memory device with redundancy includes a default array; a row redundant array block separated from the default array and provided with row redundant arrays for making up for a deficiency in a row direction; a column redundant array block separated from the default array and provided with column redundant arrays for making up for a deficiency in a column; a control block supplying a control signal commonly to the default array, row redundant array, and column redundant array; and a redundant calculation block for receiving address and control signals to generate a control signal necessary to the redundant array and to determine whether the redundant array is accessed, and to generate a signal to disable a sense amplifier of the default array during the redundant array access.

Abstract: An apparatus and method for embedding and extracting digital watermarks using a blind mode based on wavelet transform which is robust to external attacks while being capable of minimizing a degradation in picture quality caused by embedding of the watermarks. In accordance with the invention, watermarks protection of the copyright for desired data are embedded in DC component domains of wavelet-transformed domains. In accordance with the invention, embedding of watermarks in a target image corresponding to a target domain in which the watermarks are to be embedded, is achieved by generating a data stream of the watermarks in accordance with a key value selected by the user, generating index information representing positions where the watermarks are to be embedded, in accordance with a key value selected by the ser, and reflecting the watermark data stream on data values of pixels in the target image at the positions based on the index information.

Abstract: An apparatus and method for embedding and extracting digital watermarks based on wavelets which is robust to external attacks while being capable of minimizing a degradation in picture quality caused by embedding of the watermarks. The embedded watermarks embedded in DC component domains of wavelet-transformed domains can be robust to external attacks such as compression. The high-frequency dependency of pixels in a DC component domain determined as a target domain, in which watermarks are to be embedded, is calculated, in order to embed the watermarks in the target domain in the order of pixels having a higher high-frequency dependency. Accordingly, there is an advantage in that it is possible to minimize a degradation in picture quality caused by the embedding of watermarks in the DC component domain.

Abstract: A data output circuit for a semiconductor device with a level shifter and a method for outputting data using the same.

Abstract: In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.

Abstract: Methods and apparatus for performing read and write operations in a semiconductor memory device comprising an I/O (input/output) architecture comprising a separate data input bus and data output bus. In one aspect, read and write operations are sequentially performed in a same cycle using QDR2 (Quadruple Data Rate 2) in a separate input and output architecture wherein each of the input and output modes operate at a 2-bit burst mode and a double data rate (DDR) mode, thereby minimizing cycle time. In another aspect, read and write operations are sequentially performed in a same cycle using QDR4 (Quadruple Data Rate 4) in a separate input and output architecture, wherein each of the input and output modes operate at a 4-bit burst mode and a DDR mode, thereby minimizing the cycle time.

Abstract: An algebraic blending method accomplishes continuity of two n-the order curves or curved surface patch by generating a new control point of boundary by using a simple algebraic blending method in modeling a free curves/curved surface constructed by a B-spline. At a first step, a B-spline curved surface patch is obtained by using universal parametrization. At a second step, two adjacent patch to be connected with continuity is selected among the patch obtained at the first step. At a third step, at least one control point of a large patch is obtained by obtaining control points of the selected two curved surfaces and blending superposed control points. At a final step, a B-spline curved surface patch is obtained by using the obtained control points of the large patch and the two patch of the original model is replaced with the B-spline curved surface patch.

Abstract: A semiconductor memory device having redundancy with no performance penalty. The semiconductor memory device with redundancy includes a default array; a row redundant array block separated from the default array and provided with row redundant arrays for making up for a deficiency in a row direction; a column redundant array block separated from the default array and provided with column redundant arrays for making up for a deficiency in a column; a control block supplying a control signal commonly to the default array, row redundant array, and column redundant array; and a redundant calculation block for receiving address and control signals to generate a control signal necessary to the redundant array and to determine whether the redundant array is accessed, and to generate a signal to disable a sense amplifier of the default array during the redundant array access.

Abstract: In order to reduce a cycle time and enable a high-speed operation in a semiconductor memory, the memory is constructed having a multi-pipeline structure. The multi-pipeline structure, for instance, includes a three-stage pipeline, in which an additional data register is introduced between a sense amplifier and a main data line. The remaining memory structure can be configured in a manner comparable to that of a conventional two-stage pipeline semiconductor memory.

Abstract: A data transmission circuit is provided for compensating for a difference between data transmission speed occurring at start and end portions of a data line. The circuit minimizes a time delay caused by resistance/capacitance loading of the data line through which data is transmitted, thereby improving data transmission speed. The data transmission circuit of the present invention includes a compensation circuit to compensate for the time delay between the data signals at the start and end portions of the data line. The compensation circuit is adapted to amplify and rapidly develop a data signal at the end portion of the data line through which a data signal is enabled from its high state to its low state and transmitted as a data signal at the end portion of the data line.

Abstract: A data output circuit includes a periphery circuit connected between a supply voltage and a first ground voltage line and an output driver connected between a supply voltage and a second ground voltage line. The periphery circuit receives a first input signal and generates a first output signal on a node responsive to the first input signal, and the output driver receives a second input signal and the first output signal and generates a second output signal on an output pin in response thereto. A discharge circuit is coupled with the first ground voltage line wherein the discharge circuit allows current to flow from the first ground voltage line and wherein the discharge circuit blocks current flow to the first ground voltage line. Related methods are also discussed.