Abstract: A semiconductor memory apparatus and refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC) transistors. Each FBC transistor has a gate connected to a word line, a drain connected to a bit line, and a source connected to a source line. FBC transistor pairs are formed by sharing the source lines in the plurality of the floating body cell transistors. When a refresh signal is enabled, the semiconductor memory apparatus is configured to read data stored in the memory cell block by enabling a refresh read signal and then configured to rewrite the read data in the memory cell block by enabling a refresh write signal.

Abstract: An interbody fusion implant with deployable bone anchors includes a support member, a monolithic body that accommodates the support member, and a longitudinal hole along a vertical length of the support member. The support member includes a first end and a second end. The second end includes two flanges. The flanges are configured to dig into an endplate of a vertebral body. The flanges of the support member provide a location fixation on an implantation of the interbody fusion implant into the vertebral body. The support member may also include at least one of a clip shaped support member and an I-shaped support member. The I-shaped support member may allow a rigidity and a support in flexion-extension through a living-hinge positioned in a middle of the I-shaped support member. The longitudinal hole sustains loads imported on the interbody fusion implant and allows the interbody fusion implant to flex freely.

Abstract: A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first and the second driving lines, and a current controlling block configured to control a supply current provided to the first and second driving lines in response to temperature information in a writing operation.

Abstract: A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured to include first and second magnetic memory devices, whose lower electrodes are commonly connected to each other, to generate a reference current corresponding to each of the memory cells; and a sense amplification unit configured to sense and amplify the reference current and a data current corresponding to a memory cell connected to an activated word line among the word lines.

Abstract: A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first and the second driving lines, and a current controlling block configured to control a supply current provided to the first and second driving lines in response to temperature information in a writing operation.

Abstract: A semiconductor integrated circuit includes a delay line of a delay locked loop. The delay line of the delay locked loop includes a delay variation detecting unit that outputs a detection signal according to a variation in delay time using a reference clock signal, and a plurality of delay units that change a delay time according to the detection signal and delay the output of an input signal by the changed delay time.

Abstract: A screw assembly and method includes a coupling member comprising a semi-bulbous end; a fixator component that receives the semi-bulbous end of the coupling member; a resisting member mounted in the coupling member and comprising a mating member; a connection pin comprising a resisting member socket operatively connected to the mating member of the resisting member; and a blocker that engages the coupling member.

Abstract: A sliding intervertebral implant method includes a first member that connects to an intervertebral space between two adjacent vertebrae. The first member includes a pair of curved side walls connected to each of a front wall, an upper curved wall, and a lower curved wall, wherein a length of a first curved side wall is less than a length of each of a second curved side wall, the upper curved wall, and the lower curved wall, and wherein an edge of the second curved side wall is offset from an edge of the front wall. A second member is slidably attached to the first member, and includes a top and bottom curved wall each connected to an inclined side wall and a guide wall, wherein the guide wall comprises grooves, wherein the second curved side wall of the first member slides in the grooves of the guide wall.

Abstract: A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.

Abstract: An adjustable polyaxial tissue retractor includes a retraction bar including a plurality of etched teeth, a retraction blade coupled to the retraction bar, a connector including a quick release component cavity and an outwardly protruding and expandable round bulbous body, a quick release component engaged with at least one tooth of the retraction bar via a retraction bar cavity, where the quick release component is configured to loosely mate with the quick release component cavity, a saddle pin engaged within the connector via a first channel bored through the connector and contacting the bulbous body causing the bulbous body to outwardly expand, and a base including a plurality of embedded sockets and directly connected to the bulbous body, where the base receives the connector.

Abstract: A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.

Abstract: A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.

Abstract: A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first and the second driving lines, and a current controlling block configured to control a supply current provided to the first and second driving lines in response to temperature information in a writing operation.

Abstract: A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured to include first and second magnetic memory devices, whose lower electrodes are commonly connected to each other, to generate a reference current corresponding to each of the memory cells; and a sense amplification unit configured to sense and amplify the reference current and a data current corresponding to a memory cell connected to an activated word line among the word lines.

Abstract: A tissue retraction apparatus comprising a first body including a first body lower surface with a plurality of tracks embedded therein; a second body coupled to the first body that allows rotational movement of the first body relative to the second body, the second body including a second body upper surface comprising a plurality of tracks embedded therein; and a plurality of dilation components axially spaced around a dynamic opening, each dilation component comprising an arm including a top and a bottom, where the arm is coupled to an arm track of the second body and allows translational movement of the arm along the arm track; a pin fixedly coupled to the top of the arm, wherein the pin is coupled to a track of the first body and allows translational movement of the pin along the track; and a leg fixedly coupled to the bottom of the arm.

Abstract: A pedicle screw assembly and method of assembly comprises a longitudinal member; a bendable ball ring adapted to receive the longitudinal member; a poly stem comprising a bendable male bulbous end; and a connector comprising a pair of first apertures adapted to receive the poly stem; and a second aperture adapted to receive the ball ring and the longitudinal member, wherein the second aperture is transverse to the first aperture. The assembly further comprises a bone fixator component comprising a female socket adapted to receive the poly stem; and a blocker pin adapted to engage the poly stem and to secure the longitudinal member.

Abstract: A semiconductor memory apparatus and refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC) transistors. Each FBC transistor has a gate connected to a word line, a drain connected to a bit line, and a source connected to a source line. FBC transistor pairs are formed by sharing the source lines in the plurality of the floating body cell transistors. When a refresh signal is enabled, the semiconductor memory apparatus is configured to read data stored in the memory cell block by enabling a refresh read signal and then configured to rewrite the read data in the memory cell block by enabling a refresh write signal.

Abstract: An apparatus for generating a pulse which generates an internal signal. The apparatus includes a latch circuit latching an input signal to output a first signal. A clock period detector detects a period of an external clock signal to output a period detecting signal and a delay controller adjusts a delay time of the first signal to output a second signal in response to the period detecting signal. A signal generator receives the first signal and the second signal to output a pulse signal.

Abstract: A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.

Abstract: A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.