Abstract: A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.

Abstract: A dynamic screw assembly includes a screw head having a pair of diametrically opposed arms, a slot between the arms, an inwardly curved bottom portion, an outwardly protruding and expandable bulbous end extending from the inwardly curved bottom portion and an opening positioned through the bulbous end, a bumper mechanism adjacent to the screw head that adjusts an angle of the screw head to a desired location in the dynamic screw assembly, a fixation component coupled to the bumper mechanism, a saddle connection positioned in the opening and engaging the screw head and the fixation component, a longitudinal member positioned in the slot and a blocker coupled to the screw head and the longitudinal member.

Abstract: A dynamic screw assembly includes a fixation component that connects to a vertebral body, the fixation component includes at least one inlet to allow a lubricant to pass inside the fixation component, a ring member coupled to the fixation component, a stopper sealing at least one inlet, a coupling member includes an inwardly curved bottom portion and a bulbous end extending from the inwardly curved bottom portion, a bumper mechanism coupled to the fixation component and the coupling member, a longitudinal member coupled to the coupling member, and a blocker that retains the longitudinal member in the coupling member. The bulbous end includes at least one groove that houses the lubricant, and at least one slot to allow the bulbous end to fit into the fixation component and to limit a range of angulation of the coupling member with respect to the fixation component.

Abstract: A spread spectrum clock generator for sequentially modulating a source clock of a fixed frequency with a predetermined frequency range, including: a plurality of first loading units configured to delay clock edges of the source clock by a delay time corresponding to the number of unit delay steps determined by delay step control signals, wherein each of the first loading units comprises a plurality of second loading units each of which is configured to vary a delay value of each unit delay step by changing an inner interconnection configuration thereof in response to unit delay step control signals.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

Abstract: A multiple-state geometry artificial disc assembly attached to vertebrae includes a compliant load bearing spacer element having an upper curved portion and a lower curved portion, a first plate coupled on the upper curved portion of the compliant load bearing spacer element and a second plate coupled on the lower curved portion of the compliant load bearing spacer element. The first plate and the second plate preferably are of a flexible material. The first plate and the second plate transitions from a convex configuration to a concave configuration in-situ in a vertebral disc space. The upper curved portion and the lower curved portion of the compliant load bearing spacer element may include a plurality of openings. The compliant load bearing spacer element may further include a middle cylindrical portion dimensioned and configured to match a gap between the first plate and the second plate.

Abstract: A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.

Abstract: An interbody fusion implant with deployable bone anchors includes a support member, a monolithic body that accommodates the support member, and a longitudinal hole along a vertical length of the support member. The support member includes a first end and a second end. The second end includes two flanges. The flanges are configured to dig into an endplate of a vertebral body. The flanges of the support member provide a location fixation on an implantation of the interbody fusion implant into the vertebral body. The support member may also include at least one of a clip shaped support member and an I-shaped support member. The I-shaped support member may allow a rigidity and a support in flexion-extension through a living-hinge positioned in a middle of the I-shaped support member. The longitudinal hole sustains loads imported on the interbody fusion implant and allows the interbody fusion implant to flex freely.

Abstract: A delay apparatus, and a delay locked loop circuit and a semiconductor memory apparatus using the same are provided. A delay locked loop circuit includes a register controlled delay part that delays a plurality of clocks input during an initial operation by delay amounts among initial delay amounts to be varied, which are set according to initial state setting signals, and increases or decreases the set delay amounts according to a phase detecting signal after the initial operation, a phase comparator that compares a phase of any one of the plurality of clocks and a phase of any one of the plurality of clocks delayed by the register controlled delay part and outputs the phase detecting signal, and an initial state setting unit that generates the initial state setting signals.

Abstract: A clock modulation circuit includes a modulation block that receives a fixed clock generated from a reference clock and buffers the fixed clock so as to generate a modulated clock. A correction unit is provided in the modulation block to correct the duty ratio of the modulated clock.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

Abstract: A delay locked loop (DLL) of a semiconductor device has a relatively small area and low current consumption while having a function of correcting a duty ratio. The semiconductor device includes a split unit configured to receive and split a reference clock to output a first clock corresponding to a first edge of the reference clock and a second clock corresponding to a second edge, a voltage generation unit configured to generate a first voltage corresponding to a duty ratio of the first clock and a second voltage corresponding to a duty ratio of the second clock, a voltage comparison unit configured to compare levels of the first and second voltages with each other, and a clock delay unit configured to receive one of the first and second clocks to delay the received clock of which delay amount is determined in response to an output signal of the voltage comparison unit.

Abstract: A spread spectrum clock generator for sequentially modulating a source clock of a fixed frequency with a predetermined frequency range, including: a plurality of first loading units configured to delay clock edges of the source clock by a delay time corresponding to the number of unit delay steps determined by delay step control signals, wherein each of the first loading units comprises a plurality of second loading units each of which is configured to vary a delay value of each unit delay step by changing an inner interconnection configuration thereof in response to unit delay step control signals.

Abstract: An internal voltage generator for a semiconductor memory device is provided. The internal voltage generator includes a first reference voltage generator for generating a first reference voltage, a second reference voltage generator for generating a second reference voltage, a core voltage generator for raising a core voltage based on the first reference voltage, and a core voltage discharger for discharging the core voltage depending on the second reference voltage.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

Abstract: A clock modulation circuit includes a modulation block that receives a fixed clock generated from a reference clock and buffers the fixed clock so as to generate a modulated clock. A correction unit is provided in the modulation block to correct the duty ratio of the modulated clock.

Abstract: A delay apparatus, and a delay locked loop circuit and a semiconductor memory apparatus using the same are provided. A delay locked loop circuit includes a register controlled delay part that delays a plurality of clocks input during an initial operation by delay amounts among initial delay amounts to be varied, which are set according to initial state setting signals, and increases or decreases the set delay amounts according to a phase detecting signal after the initial operation, a phase comparator that compares a phase of any one of the plurality of clocks and a phase of any one of the plurality of clocks delayed by the register controlled delay part and outputs the phase detecting signal, and an initial state setting unit that generates the initial state setting signals.

Abstract: A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.

Abstract: A semiconductor integrated circuit includes a delay line of a delay locked loop. The delay line of the delay locked loop includes a delay variation detecting unit that outputs a detection signal according to a variation in delay time using a reference clock signal, and a plurality of delay units that change a delay time according to the detection signal and delay the output of an input signal by the changed delay time.

Abstract: An apparatus for generating a pulse which generates an internal signal. The apparatus includes a latch circuit latching an input signal to output a first signal. A clock period detector detects a period of an external clock signal to output a period detecting signal and a delay controller adjusts a delay time of the first signal to output a second signal in response to the period detecting signal. A signal generator receives the first signal and the second signal to output a pulse signal.