Patents by Inventor Young-Hoon SON

Young-Hoon SON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12219774
    Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: February 4, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Jae Lee, Jin Do Byun, Young-Hoon Son, Young Don Choi, Pan Suk Kwak, Myung Hun Lee, Jung Hwan Choi
  • Patent number: 12211581
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: January 28, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
  • Patent number: 12206131
    Abstract: A battery module according to the present disclosure includes a plurality of cylindrical battery cells including a gas vent configured to discharge an internal gas and a busbar plate including a negative electrode connection terminal extending from an edge of a connection opening and having the extended part in contact with a negative electrode terminal to electrically connect the plurality of cylindrical battery cells wherein among a positive electrode connection terminal and the negative electrode connection terminal, the connection terminal in contact with a positive electrode terminal or a negative electrode terminal that is not opened by the gas vent includes a fuse portion configured to blow when a predetermined current or above flows from the cylindrical battery cell, the fuse portion having a bent structure that is bent in a horizontal direction at least once.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: January 21, 2025
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Han-Yong Jeong, Suk-Hoon Lee, Young-Su Son
  • Publication number: 20240404570
    Abstract: A method of training a memory device is provided. In first to third DCA training steps, a score for each of first to third DCA code combinations is calculated based on an eye window size of a data signal, and in response to a tie occurring among scores, a DCA code combination is selected based on the sum of an even-eye window minimum value and an odd-eye window minimum value of the data signal.
    Type: Application
    Filed: February 19, 2024
    Publication date: December 5, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ki-Seok PARK, Do-Han KIM, Minsu BAE, Chang-Hyun BAE, Young-Hoon SON, Hye-Seung YU, Yoenhwa LEE, Daihyun LIM, Insu CHOI, Kideok HAN
  • Publication number: 20240321338
    Abstract: A training method of a memory device adjusting an eye window of a data signal in response to a duty cycle adjuster (DCA) includes performing a first training operation that selects a first DCA code corresponding to a first internal clock signal having a phase difference of 180° relative to a reference internal clock signal, and performing a second training operation that selects a second DCA code and a third DCA code respectively corresponding to a second internal clock signal and a third internal clock signal having a phase difference of 90° and 270° relative to reference internal clock signal. In the first training operation, the eye window size of the data signal is measured in units of two unit intervals, and in the second training operation, the eye window size of the data signal is measured in units of one unit interval.
    Type: Application
    Filed: December 5, 2023
    Publication date: September 26, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kideok HAN, Ki-Seok PARK, Young-Hoon SON, Do-Han KIM, Min-Su BAE, Yoenhwa LEE, Insu CHOI
  • Publication number: 20240241011
    Abstract: A method for diagnosing a bearing fault on the basis of a current signal, and a device for performing the method, can include the steps, performed by a bearing failure diagnostic device, of: receiving a motor three-phase current signal; denoising the motor three-phase current signal; converting the denoised motor three-phase current signal to a single-phase current signal; determining a characteristic factor on the basis of the single-phase current signal; and determining, on the basis of the characteristic factor, whether a bearing fault exists.
    Type: Application
    Filed: April 27, 2022
    Publication date: July 18, 2024
    Inventors: Tae Wan HWANG, Young Hoon SON, Young June BAN, Woo Cheol LIM
  • Publication number: 20230280782
    Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 7, 2023
    Inventors: Junyoung PARK, YOUNG-HOON SON, HYUN-YOON CHO, YOUNGDON CHOI, JUNGHWAN CHOI
  • Patent number: 11687114
    Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: June 27, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junyoung Park, Young-Hoon Son, Hyun-Yoon Cho, Youngdon Choi, Junghwan Choi
  • Publication number: 20230066632
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Application
    Filed: October 18, 2022
    Publication date: March 2, 2023
    Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
  • Patent number: 11508420
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: November 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
  • Patent number: 11475930
    Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: October 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hoon Son, Si-Hong Kim, Chang-Kyo Lee, Jung-Hwan Choi, Kyung-Soo Ha
  • Patent number: 11461176
    Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Young Park, Young-Hoon Son, Hyun-Yoon Cho, Young Don Choi, Jung Hwan Choi
  • Publication number: 20220157845
    Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.
    Type: Application
    Filed: July 26, 2021
    Publication date: May 19, 2022
    Inventors: MIN JAE LEE, Jin Do Byun, Young-Hoon Son, Young Don Choi, Pan Suk Kwak, Myung Hun Lee, Jung Hwan Choi
  • Publication number: 20220138045
    Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.
    Type: Application
    Filed: August 10, 2021
    Publication date: May 5, 2022
    Inventors: Jun Young PARK, Young-Hoon SON, Hyun-Yoon CHO, Young Don CHOI, Jung Hwan CHOI
  • Patent number: 11244926
    Abstract: A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Hoon Son, Jung-Hwan Choi, Seok-Hun Hyun
  • Publication number: 20210405683
    Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.
    Type: Application
    Filed: January 8, 2021
    Publication date: December 30, 2021
    Inventors: Junyoung PARK, YOUNG-HOON SON, HYUN-YOON CHO, YOUNGDON CHOI, JUNGHWAN CHOI
  • Patent number: 11169711
    Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: November 9, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SNU R&D FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Seong-Il O, Nam Sung Kim, Young-Hoon Son, Chan-Kyung Kim, Ho-Young Song, Jung Ho Ahn, Sang-Joon Hwang
  • Publication number: 20210327476
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 21, 2021
    Inventors: DONGHUN LEE, Daesik MOON, Young-Soo SOHN, Young-Hoon SON, Ki-Seok OH, Changkyo LEE, Hyun-Yoon CHO, Kyung-Soo HA, Seokhun HYUN
  • Publication number: 20210233575
    Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 29, 2021
    Inventors: YOUNG-HOON SON, SI-HONG KIM, CHANG-KYO LEE, JUNG-HWAN CHOI, KYUNG-SOO HA
  • Patent number: 11062744
    Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun