Abstract: A substrate processing apparatus includes: a nozzle unit configured to discharge a processing liquid to a substrate; a pipe connected to the nozzle unit and a processing liquid supply unit supplying the processing liquid; a charge amount control unit disposed at the pipe, including a filter unit charged with positive charges or negative charges, and including at least one of a control valve, controlling a flow rate of the processing liquid passing through an inside of the filter unit, and a power supply unit, applying a voltage to the filter unit, to control a charge amount of the processing liquid; and a control unit connected to the charge amount control unit.

Abstract: An image sensor substrate according to an embodiment includes: an insulating layer; and a conductive pattern part disposed on the insulating layer, wherein the insulating layer includes: a first insulating part: and a second insulating part disposed surrounding a periphery of the first insulating part and spaced apart from the first insulating part with a first open region interposed therebetween, and the conductive pattern part includes: a first conductive pattern part disposed on the first insulating part; a second conductive pattern part disposed on the second insulating part; and an extension pattern part disposed on the first open region and interconnecting the first and second conductive pattern parts, wherein the extension pattern part includes a bent portion disposed on a corner region of the first open region.

Abstract: Disclosed is a headrest having a speaker, the headrest including: a headrest frame having a rear surface to which a driving module is coupled so that the headrest frame is movable forwards, rearwards, or vertically in response to operation of the driving module, the headrest frame having a front surface formed with a mounting space recessed rearwards; a speaker, inserted into the mounting space in the headrest frame, provided with an output portion facing forwards and outputting sound, the speaker having a rear side closed by the headrest frame; a foam pad, mounted on the front surface of the headrest frame so as to cover the headrest frame and the speaker, having formed therein a first through hole outputting sound forwards at a position corresponding to the output portion; and a covering configured to cover the front surface of the foam pad and forming the front exterior of the headrest.

Abstract: An ultrasonic transmission circulation system of an ultrasound treatment head and method therefor are provided. In the system and the method therefor according to an embodiment, the supply, discharge, and circulation of the ultrasonic transmission medium with respect to the ultrasound treatment head are all possible by means of a single pump. Further, in the system and the method therefor according to an embodiment, a single system is driven by changing a passage through selective opening and closing of the valves in the system according to the material of a membrane, so that there is no need to drive a separate system for each membrane material.

Abstract: A positioning arm apparatus for an ultrasound head is provided. The positioning arm apparatus for an ultrasound head according to an embodiment may constantly move the ultrasound head without change in height of the ultrasound head according to a moving distance by simultaneous rotation at two positions and tilting motion at one position. Also, the positioning arm apparatus may be miniaturized and lightweight since it is operated with a mechanical mechanism, and may provide strong fixing strong and easy maneuverability.

Abstract: A training method of a memory device adjusting an eye window of a data signal in response to a duty cycle adjuster (DCA) includes performing a first training operation that selects a first DCA code corresponding to a first internal clock signal having a phase difference of 180° relative to a reference internal clock signal, and performing a second training operation that selects a second DCA code and a third DCA code respectively corresponding to a second internal clock signal and a third internal clock signal having a phase difference of 90° and 270° relative to reference internal clock signal. In the first training operation, the eye window size of the data signal is measured in units of two unit intervals, and in the second training operation, the eye window size of the data signal is measured in units of one unit interval.

Abstract: An airbag chute-integrated crash pad assembly includes: a main core that includes a door portion expanding when an airbag expands, and a cover portion mounted on a dash board. In particular, the main core is formed with a reinforcement portion extending downward from a lower surface of the cover portion, and the door portion and the cover portion are separated by a hinge groove that is formed in a lower surface of the main core and forms an expansion line. The reinforcement portion is combined with an airbag accommodation body that accommodates a passenger airbag (PAB). Thus, process optimization can be realized by omitting a process of machining a score and fusing a PAB chute, and also a problem of damage to the PAB chute can be solved.

Abstract: A positioning arm apparatus for an ultrasound head is provided. The positioning arm apparatus for an ultrasound head according to an embodiment may constantly move the ultrasound head without change in height of the ultrasound head according to a moving distance by simultaneous rotation at two positions and tilting motion at one position. Also, the positioning arm apparatus may be miniaturized and lightweight since it is operated with a mechanical mechanism, and may provide strong fixing strong and easy maneuverability.

Abstract: A method for diagnosing a bearing fault on the basis of a current signal, and a device for performing the method, can include the steps, performed by a bearing failure diagnostic device, of: receiving a motor three-phase current signal; denoising the motor three-phase current signal; converting the denoised motor three-phase current signal to a single-phase current signal; determining a characteristic factor on the basis of the single-phase current signal; and determining, on the basis of the characteristic factor, whether a bearing fault exists.

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.

Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.

Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.

Abstract: A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.