Abstract: A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.

Abstract: A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.

Abstract: The present invention relates to a tandem organic light-emitting element, more particularly to a tandem organic light-emitting element which may decrease a driving voltage in a driving region of a charge generation layer by sequentially laminating an electronics layer, which is doped with a metal dopant, and an electronics layer, which is doped with an organic dopant, on one side of the charge generation layer, thereby having increased power efficiency and life span.

Abstract: A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Abstract: A memory device may include a memory cell array, a bloom-filter circuit, a cache memory circuit, and a selecting circuit. The bloom-filter circuit may be configured to output a determination result signal that indicates that there is a possibility that a received address is one of failed addresses corresponding to failed cells of the memory cell array. The cache memory circuit may be configured to, store the failed addresses and a first set of data corresponding to the respective failed addresses, and configured to, when the determination result signal indicates a possibility, provide a comparison result signal by determining whether received address coincides with one of the failed addresses. The selecting circuit may be configured to output either first data of the first set of data or second data of the memory cell array corresponding to the received address based on determination result signal and comparison result signal.

Abstract: A wafer carrier including a case having an opening at one end, slots disposed in the case and receiving wafers, and a wireless communication circuitry disposed on an inner sidewall of the case and configured to detect humidity of a gas contained in the case may be provided. The wireless communication circuitry may be further configured to compare the detected humidity with a threshold humidity predetermined, and transmit a first warning signal to an external host via wireless communication when the detected humidity is greater than the threshold humidity.

Abstract: The present invention relates to a tandem type organic light emitting device and, more specifically, to a tandem type organic light emitting device which exhibits low operation voltage, high power efficiency and an excellent color rendering index (CRI). To this end, the present invention provides a tandem type organic light emitting device, the device comprising: a base substrate; a first electrode formed on the base substrate; a second electrode formed to oppose the first electrode; and first to third organic light emitting layers formed in sequence from the first electrode, between the first electrode and the second electrode. The first organic light emitting layer comprises a first light emitting layer for emitting blue light, the second organic light emitting layer comprises a second light emitting layer for emitting yellow light, and the third organic light emitting layer comprises a third light emitting layer for emitting red light.

Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

Abstract: The present invention relates to a tandem organic light-emitting element, more particularly to a tandem organic light-emitting element which may decrease a driving voltage in a driving region of a charge generation layer by sequentially laminating an electronics layer, which is doped with a metal dopant, and an electronics layer, which is doped with an organic dopant, on one side of the charge generation layer, thereby having increased power efficiency and life span.

Abstract: A memory device includes a first memory cell, a second memory cell, a precharge circuit, a sense amplifier, a switch circuit, and a controller. The first memory cell is connected to a first bit line, the second memory cell is connected to a second bit line, and the precharge circuit connected between the first bit line and the second bit line. The sense amplifier includes a first input terminal and a second input terminal. The switch circuit is connected to the first bit line and the first input terminal and to the second bit line and the second input terminal and is configured to control a connection between the first bit line and the first input terminal and a connection between the second bit line and the second input terminal in response to a switch signal. The controller is configured to generate the switch signal in response to a command.

Abstract: A memory device includes a first memory cell, a second memory cell, a precharge circuit, a sense amplifier, a switch circuit, and a controller. The first memory cell is connected to a first bit line, the second memory cell is connected to a second bit line, and the precharge circuit connected between the first bit line and the second bit line. The sense amplifier includes a first input terminal and a second input terminal. The switch circuit is connected to the first bit line and the first input terminal and to the second bit line and the second input terminal and is configured to control a connection between the first bit line and the first input terminal and a connection between the second bit line and the second input terminal in response to a switch signal. The controller is configured to generate the switch signal in response to a command.

Abstract: A memory device may include a memory cell array, a bloom-filter circuit, a cache memory circuit, and a selecting circuit. The bloom-filter circuit may be configured to output a determination result signal that indicates that there is a possibility that a received address is one of failed addresses corresponding to failed cells of the memory cell array. The cache memory circuit may be configured to, store the failed addresses and a first set of data corresponding to the respective failed addresses, and configured to, when the determination result signal indicates a possibility, provide a comparison result signal by determining whether received address coincides with one of the failed addresses. The selecting circuit may be configured to output either first data of the first set of data or second data of the memory cell array corresponding to the received address based on determination result signal and comparison result signal.

Abstract: The present invention relates to a pharmaceutical composition for preventing or treating a muscle wasting-related disease comprising diaminodiphenylsulfone (Dapsone; DDS) or a pharmaceutically acceptable salt thereof as an active ingredient. The composition according to the present invention may be effectively used to prevent or treat a muscle wasting-related disease by increasing muscle mass, preventing muscle loss and effectively restoring muscle function.

Abstract: The present invention relates to a pharmaceutical composition for preventing or treating a muscle wasting-related disease comprising diaminodiphenylsulfone (Dapsone; DDS) or a pharmaceutically acceptable salt thereof as an active ingredient. The composition according to the present invention may be effectively used to prevent or treat a muscle wasting-related disease by increasing muscle mass, preventing muscle loss and effectively restoring muscle function.

Abstract: The present invention relates to a pharmaceutical composition for preventing or treating a disease with bone mass loss, which comprises diaminodiphenylsulfone (Dapsone; DDS) or a pharmaceutically acceptable salt thereof as an active ingredient. The composition according to the present invention may be effectively used to prevent or treat a disease with bone mass loss such as osteopenia or osteoporosis by effectively restoring the reduction of bone density and bone mass.

Abstract: A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter than each path of a second set of data paths from each of the plurality of second memory cell arrays to the corresponding DQ pad. Each of the plurality of first memory cell arrays is a designated first-speed access cell array and each of the plurality of second memory cell arrays is a designated second-speed access cell array, the second-speed being slower than the first-speed. A size of the each of the plurality of first memory cell arrays is smaller than a size of the each of the plurality of second memory cell arrays.