Patents by Inventor Young-Hoon SON
Young-Hoon SON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210405683Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.Type: ApplicationFiled: January 8, 2021Publication date: December 30, 2021Inventors: Junyoung PARK, YOUNG-HOON SON, HYUN-YOON CHO, YOUNGDON CHOI, JUNGHWAN CHOI
-
Patent number: 11169711Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.Type: GrantFiled: July 29, 2019Date of Patent: November 9, 2021Assignees: SAMSUNG ELECTRONICS CO., LTD., SNU R&D FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATIONInventors: Seong-Il O, Nam Sung Kim, Young-Hoon Son, Chan-Kyung Kim, Ho-Young Song, Jung Ho Ahn, Sang-Joon Hwang
-
Publication number: 20210327476Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.Type: ApplicationFiled: June 23, 2021Publication date: October 21, 2021Inventors: DONGHUN LEE, Daesik MOON, Young-Soo SOHN, Young-Hoon SON, Ki-Seok OH, Changkyo LEE, Hyun-Yoon CHO, Kyung-Soo HA, Seokhun HYUN
-
Publication number: 20210233575Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.Type: ApplicationFiled: January 5, 2021Publication date: July 29, 2021Inventors: YOUNG-HOON SON, SI-HONG KIM, CHANG-KYO LEE, JUNG-HWAN CHOI, KYUNG-SOO HA
-
Patent number: 11062744Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.Type: GrantFiled: January 30, 2019Date of Patent: July 13, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
-
Patent number: 10936261Abstract: A printing method and a printing system are provided.Type: GrantFiled: July 2, 2018Date of Patent: March 2, 2021Assignee: Hewlett-Packard Development Company, L.P.Inventors: In Cheon Park, Gi Won Seo, Young Hoon Son, Jong Ha Yun, Byeong Jin Lee
-
Patent number: 10916279Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.Type: GrantFiled: April 14, 2020Date of Patent: February 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hoon Son, Si-Hong Kim, Chang-Kyo Lee, Jung-Hwan Choi, Kyung-Soo Ha
-
Patent number: 10763242Abstract: A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.Type: GrantFiled: June 1, 2018Date of Patent: September 1, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Hoon Son, Jung-Hwan Choi, Seok-Hun Hyun
-
Publication number: 20200243123Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Inventors: YOUNG-HOON SON, SI-HONG KIM, CHANG-KYO LEE, JUNG-HWAN CHOI, KYUNG-SOO HA
-
Patent number: 10692554Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.Type: GrantFiled: December 19, 2019Date of Patent: June 23, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hoon Son, Si-Hong Kim, Chang-Kyo Lee, Jung-Hwan Choi, Kyung-Soo Ha
-
Patent number: 10665558Abstract: A semiconductor memory includes a plurality of first pads arranged in a first direction, a plurality of second pads arranged parallel to the plurality of first pads and in the first direction, a plurality of third pads arranged in a second direction perpendicular to the first direction, and a plurality of fourth pads arranged in the second direction. The semiconductor memory further includes first interconnection wires extending from the plurality of first pads in the second direction, the first interconnection wires being connected to the plurality of third pads, and second interconnection wires extending from the plurality of second pads in an opposite direction to the second direction, the second interconnection wires being connected to the plurality of fourth pads.Type: GrantFiled: July 16, 2018Date of Patent: May 26, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sihong Kim, Young-Hoon Son, Taeyoung Oh, Kyung-Soo Ha
-
Publication number: 20200135247Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.Type: ApplicationFiled: December 19, 2019Publication date: April 30, 2020Inventors: YOUNG-HOON SON, SI-HONG KIM, CHANG-KYO LEE, JUNG-HWAN CHOI, KYUNG-SOO HA
-
Publication number: 20200073606Abstract: A printing method and a printing system are provided.Type: ApplicationFiled: July 2, 2018Publication date: March 5, 2020Inventors: In Cheon Park, Gi Won Seo, Young Hoon Son, Jong Ha Yun, Byeong Jin Lee
-
Patent number: 10566038Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.Type: GrantFiled: March 12, 2018Date of Patent: February 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hoon Son, Si-Hong Kim, Chang-Kyo Lee, Jung-Hwan Choi, Kyung-Soo Ha
-
Patent number: 10566968Abstract: An output driver includes a pre-driver receiving a driver control code to generate a pull-up control signal or a pull-down control signal in response to data while a read operation is performed, an on-die termination controller receiving a first on-die termination control code to generate a first on-die termination control signal in response to an on-die termination enable signal while a write operation is performed, and a main driver including a pull-up n-channel metal-oxide-semiconductor (NMOS) driver generating high-level output data in response to the pull-up control signal while the read operation is performed, and terminating high-level input data with a first high voltage and terminating low-level input data with a first low voltage in response to the first on-die termination control signal while the write operation is performed, and a pull-down NMOS driver generating low-level output data in response to the pull-down control signal while the read operation is performed.Type: GrantFiled: March 20, 2019Date of Patent: February 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Hoon Son, Jung Hwan Choi, Seok Hun Hyun
-
Publication number: 20200044645Abstract: An output driver includes a pre-driver receiving a driver control code to generate a pull-up control signal or a pull-down control signal in response to data while a read operation is performed, an on-die termination controller receiving a first on-die termination control code to generate a first on-die termination control signal in response to an on-die termination enable signal while a write operation is performed, and a main driver including a pull-up n-channel metal-oxide-semiconductor (NMOS) driver generating high-level output data in response to the pull-up control signal while the read operation is performed, and terminating high-level input data with a first high voltage and terminating low-level input data with a first low voltage in response to the first on-die termination control signal while the write operation is performed, and a pull-down NMOS driver generating low-level output data in response to the pull-down control signal while the read operation is performed.Type: ApplicationFiled: March 20, 2019Publication date: February 6, 2020Inventors: YOUNG HOON SON, JUNG HWAN CHOI, SEOK HUN HYUN
-
Publication number: 20190362763Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.Type: ApplicationFiled: January 30, 2019Publication date: November 28, 2019Inventors: Donghun Lee, Daesik Moon, Young-Soo Sohn, Young-Hoon Son, Ki-Seok Oh, Changkyo Lee, Hyun-Yoon Cho, Kyung-Soo Ha, Seokhun Hyun
-
Publication number: 20190354292Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.Type: ApplicationFiled: July 29, 2019Publication date: November 21, 2019Applicants: SNU R&DB FOUNDATION, WISCONSIN ALUMNI RESEARCH FOUNDATIONInventors: Seong-Il O, Nam Sung KIM, Young-Hoon SON, Chan-Kyung KIM, Ho-Young SONG, Jung Ho AHN, Sang-Joon HWANG
-
Patent number: 10424497Abstract: A wafer carrier including a case having an opening at one end, slots disposed in the case and receiving wafers, and a wireless communication circuitry disposed on an inner sidewall of the case and configured to detect humidity of a gas contained in the case may be provided. The wireless communication circuitry may be further configured to compare the detected humidity with a threshold humidity predetermined, and transmit a first warning signal to an external host via wireless communication when the detected humidity is greater than the threshold humidity.Type: GrantFiled: June 21, 2017Date of Patent: September 24, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Bum-Soo Kim, Philwoong Jung, Yoonmi Lee, Hangryong Lim, Manyoung Shin, Young Hoon Son
-
Patent number: 10416896Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.Type: GrantFiled: May 23, 2017Date of Patent: September 17, 2019Assignees: Samsung Electronics Co., Ltd., SNU R&DB Foundation, Wisconsin Alumni Research FoundationInventors: Seong-Il O, Nam Sung Kim, Young-Hoon Son, Chan-Kyung Kim, Ho-Young Song, Jung Ho Ahn, Sang-Joon Hwang