Abstract: An image sensor may include a lower device that includes logic transistors, an intermediate device that is formed over the lower device and includes a Correlated Double Sampling (CDS) circuit and a capacitor, and an upper device that is formed over the intermediate device and includes a photodiode, a floating diffusion region, and a transfer gate electrode.

Abstract: An image sensor may include a photoelectric conversion element, a transfer transistor formed over the photoelectric conversion element, and a reset transistor formed over the photoelectric conversion element, formed substantially at the same level as the transfer transistor, and spaced apart from the transfer transistor by a gap, wherein the transfer transistor and the reset transistor are configured symmetrical to each other with respect to the gap.

Abstract: An image sensor may include: a photoelectric conversion element suitable for generating a photo charge in response to incident light; and a transfer transistor suitable for transferring the photo charge generated by the photoelectric conversion element to a floating diffusion in response to a transfer signal, the transfer transistor comprising a first transfer gate formed over the photoelectric conversion element; an opening formed in the first transfer gate and exposing the photoelectric conversion element; a second transfer gate formed in the opening; and a channel layer interposed between the first and second transfer gates and between the photoelectric conversion element and the second transfer gate.

Abstract: An image sensor may include: a photoelectric conversion element including a second conductive layer formed over a first conductive layer; an insulating layer and a third conductive layer which are sequentially formed over the second conductive layer; an opening exposing the second conductive layer through the third conductive layer and the insulating layer; a channel layer formed along the surface of the opening, and including first and second channel layers which are coupled to each other while having different conductivity types; and a transfer gate formed over the channel layer to fill the opening, and partially formed over the third conductive layer.

Abstract: This technology relates to an image sensor. The image sensor may include a substrate including a photoelectric conversion element; a pillar formed over the photoelectric conversion element and having a concave-convex sidewall; a channel film formed along a surface of the pillar and for having at least one end coupled to the photoelectric conversion element; and a transfer gate formed over the channel film.

Abstract: An image sensor includes a photoelectric conversion element, including a first impurity region and a second impurity region, wherein the first impurity region contacts a first surface of a substrate, wherein the second impurity region has conductivity complementary to the first impurity region and is formed in the substrate and below the first impurity region; a pillar formed over the photoelectric conversion element; a transfer gate formed over the photoelectric conversion element to surround the pillar; and a channel layer formed between the transfer gate and the pillar and contacting the photoelectric conversion element, wherein the channel layer contacts the first impurity region and has the same conductivity as the second impurity region.

Abstract: A multi-bus system includes a first layer bus, a second layer bus connected to the first layer bus, at least one master device, and a decoder. The at least one master device is configured to be connected to the first layer bus via a first data path, and configured to be connected to the second layer bus via a second data path. The decoder is configured to directly connect the at least one master device to the first layer bus via the first data path, and directly connect the at least one master device to the second layer bus via the second data path.

Abstract: An image sensor includes a photoelectric conversion element including a first impurity region and a second impurity region, wherein the first impurity region contacts a first surface of a substrate, wherein the second impurity region has conductivity complementary to the first impurity region and is formed in the substrate and below the first impurity region; a pillar formed over the photoelectric conversion element; a transfer gate formed over the photoelectric conversion element to surround the pillar; and a channel layer formed between the transfer gate and the pillar and contacting the photoelectric conversion element, wherein the channel layer contacts the first impurity region and has the same conductivity as the second impurity region.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: A system on chip (SoC) includes a system bus; a plurality of intellectual properties (IPs) outputting bus signals via the system bus; and one or more checkers disposed to correspond to at least some of the plurality of IPs, wherein the checker includes: a first environment setting register for setting information about a check target and list, on which a bus protocol check operation will be performed, wherein the setting may be variable according to an access from outside via the system bus; and a check logic receiving the bus signal and performing a bus protocol check operation on a signal included in the bus signal according to the information set in the first environment setting register.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: A nonvolatile memory device includes a tunneling region and an erase region formed over a substrate, a selection gate formed over the substrate to overlap with the tunneling region, a floating gate formed over the substrate to be disposed adjacent to the selection gate with a gap therebetween and to overlap with the tunneling region and the erase region, and a charge blocking layer filling the gap.

Abstract: In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Abstract: This technology provides a non-volatile memory device and a method of manufacturing the same, which may prevent an over-erase phenomenon and also increase the degree of integration, In an aspect, the non-volatile memory device includes a select gate formed over a substrate, a plurality of floating gates laterally formed with respect to the select gate and spaced apart from each other, to be independently programmable, and a plurality of junctions formed in the substrate and arranged to be controllable by the respective floating gates.

Abstract: A nonvolatile memory device includes a memory gate including a memory layer provided over a substrate and a gate electrode provided over the memory layer, the memory gate having first and second opposing sidewalls disposed on first and second sides of the memory gate, respectively; first and second select gates disposed on the first and second sidewalls of the memory gate; a source region formed in the substrate proximate to the first side of the memory gate; a drain region formed in the substrate proximate to the second side of the memory gate; and a gate contact coupled to the gate electrode of the memory gate and to the first select gate, or the second select gate, or both.

Abstract: A nonvolatile memory device includes a tunneling region and an erase region formed over a substrate, a selection gate formed over the substrate to overlap with the tunneling region, a floating gate formed over the substrate to be disposed adjacent to the selection gate with a gap therebetween and to overlap with the tunneling region and the erase region, and a charge blocking layer filling the gap.

Abstract: A toothbrush having needle-shaped bristles on the head portion is configured such that the differences in height between the longer and shorter bristles is 1 to 4 mm, the end points of the longer bristles are 0.01 to 0.03 mm in diameter, the end points of the shorter bristles are 0.03 to 0.08 mm in diameter, the taper lengths of the longer bristles are 4 to 8 mm, the taper lengths of the shorter bristles are 2 to 6 mm, and the differences in taper length between the longer and shorter bristles is 1 to 4 mm. The toothbrush provides superior teeth and gum contact force unique to a toothbrush having needle-shaped bristles and at the same time also provides superior cleaning performance for the surface of teeth thanks to the action of the shorter bristles having relatively large diameters at end points and relatively short taper lengths.

Abstract: A system on chip (SoC) includes a system bus; a plurality of intellectual properties (IPs) outputting bus signals via the system bus; and one or more checkers disposed to correspond to at least some of the plurality of IPs, wherein the checker includes: a first environment setting register for setting information about a check target and list, on which a bus protocol check operation will be performed, wherein the setting may be variable according to an access from outside via the system bus; and a check logic receiving the bus signal and performing a bus protocol check operation on a signal included in the bus signal according to the information set in the first environment setting register.

Abstract: A multi-bus system includes a first layer bus, a second layer bus connected to the first layer bus, at least one master device, and a decoder. The at least one master device is configured to be connected to the first layer bus via a first data path, and configured to be connected to the second layer bus via a second data path. The decoder is configured to directly connect the at least one master device to the first layer bus via the first data path, and directly connect the at least one master device to the second layer bus via the second data path.

Abstract: A nonvolatile memory device includes a memory gate including a memory layer provided over a substrate and a gate electrode provided over the memory layer, the memory gate having first and second opposing sidewalls disposed on first and second sides of the memory gate, respectively; first and second select gates disposed on the first and second sidewalls of the memory gate; a source region formed in the substrate proximate to the first side of the memory gate; a drain region formed in the substrate proximate to the second side of the memory gate; and a gate contact coupled to the gate electrode of the memory gate and to the first select gate, or the second select gate, or both.