Abstract: A high-voltage battery control apparatus includes a plurality of high-voltage battery controllers configured to respectively monitor states of a plurality of high-voltage batteries included in one high-voltage battery pack depending on a predetermined period for monitoring the high-voltage battery pack, wherein the high-voltage battery controllers are configured to transition state of the plurality of high-voltage battery controllers together to an end state when a high-voltage battery controller among the high-voltage battery controllers, which has completed a monitoring operation, first waits until all monitoring operations of the high-voltage battery controllers that have not yet completed monitoring operations are completed and then all the monitoring operations of the high-voltage battery controllers are completed.

Abstract: A method of a wearable device displaying icons is provided. The method includes displaying a plurality of circular icons comprising a first circular icon located in a center area of a touch display in a first size and a second circular icon located outside of the center area of the touch display in a second size smaller than the first size, and based on a direction of a touch input received on the touch display, moving the plurality of circular icons such that the first circular icon is moved to a first position located outside of the center area of the touch display and the second circular icon is moved from a second position located outside the center area of the touch display to the center area of the touch display and enlarged in size from the second size to the first size.

Abstract: Disclosed is a method for manufacturing a high-density neural probe including needles having various forms. The method, in which only a photolithography process and an etching process are used, simplifies a manufacturing process of the neural probe, minimizes changes in the characteristics of the neural probe depending on process equipment or conditions, and may thus ensure a high yield, thereby being advantageous in terms of commercialization. In addition, various forms of needles may be manufactured depending on the shape of patterns included in a mask, the height of the needles may be controlled by adjusting the size of the patterns and the gap between the patterns, and thereby, a neural probe having a plurality of needles having different heights may be manufactured.

Abstract: The present invention relates to: a method for forming an ohmic contact of a GaN-based electronic device, comprising the steps of (A) irradiating an ion beam at a GaN-based electronic device to form an ion region in one part of the inside of the GaN-based electronic device, (B) forming an electrode layer on a part, corresponding to the ion region, of the surface of the GaN-based electronic, device, and (C) thermally treating the GaN-based electronic device on which the electrode layer is formed; and an ohmic contact of a GaN-based electronic device manufactured by the method for forming an ohmic contact of a GaN-based electronic device.

Abstract: The present invention relates to: a method for manufacturing a GaN-based power device, the method comprising a step of irradiating particle beams onto a silicon substrate of a GaN-based power device, in which the silicon substrate is included; and a GaN-based power device manufactured by the method for manufacturing a GaN-based power device.

Abstract: The present invention relates to a betavoltaic battery comprising: a substrate; an intrinsic semiconductor unit disposed on the substrate; an N-type semiconductor unit and a P-type semiconductor unit that are disposed on at least a portion of a surface of the intrinsic semiconductor unit and arranged alternately; and beta ray sources that are disposed on the N-type semiconductor unit and the P-type semiconductor unit. The present invention also relates to a method for manufacturing a betavoltaic battery, comprising the steps of: (A) forming an intrinsic semiconductor unit on a substrate; (B) forming an N-type semiconductor unit and a P-type semiconductor unit alternately by irradiating at least a portion of the surface of the intrinsic semiconductor unit with an ion beam; and (C) disposing a beta ray source on the N-type semiconductor unit and the P-type semiconductor unit.

Abstract: A semiconductor memory device includes a memory region including a plurality of memory blocks, and suitable for outputting first and second read data from first and second memory blocks among the plurality of memory blocks based on first and second read control signals and a read address signal; a scheduler suitable for outputting a read scheduling signal based on the first and second read control signals; and an output driver suitable for outputting the first and second read data by a predetermined burst length alternately twice or more to a data pad based on a mode signal, wherein the first read data are outputted to the data pad according to a first burst sequence, and the second read data are outputted to the data pad according to a second burst sequence, based on the read scheduling signal.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: An image display device including a display configured to display a first image is provided. The image display device includes a controller configured to generate a second image by enlarging a part of the first image displayed in a first region of the display and to control the display to display a part of the second image in the first region, and a sensor configured to sense a user input for moving the second image. In response to the user input, the controller is configured to control the display to move and display the second image, within the first region.

Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.

Abstract: A semiconductor memory device includes a memory region including a plurality of memory blocks, and suitable for outputting first and second read data from first and second memory blocks among the plurality of memory blocks based on first and second read control signals and a read address signal; a scheduler suitable for outputting a read scheduling signal based on the first and second read control signals; and an output driver suitable for outputting the first and second read data by a predetermined burst length alternately twice or more to a data pad based on a mode signal, wherein the first read data are outputted to the data pad according to a first burst sequence, and the second read data are outputted to the data pad according to a second burst sequence, based on the read scheduling signal.

Abstract: An image display device including a display configured to display a first image is provided. The image display device includes a controller configured to generate a second image by enlarging a part of the first image displayed in a first region of the display and to control the display to display a part of the second image in the first region, and a sensor configured to sense a user input for moving the second image. In response to the user input, the controller is configured to control the display to move and display the second image, within the first region.

Abstract: A semiconductor memory device includes a memory region including a plurality of memory blocks, and suitable for outputting first and second read data from first and second memory blocks among the plurality of memory blocks based on first and second read control signals and a read address signal; a scheduler suitable for outputting a read scheduling signal based on the first and second read control signals; and an output driver suitable for outputting the first and second read data by a predetermined burst length alternately twice or more to a data pad based on a mode signal, wherein the first read data are outputted to the data pad according to a first burst sequence, and the second read data are outputted to the data pad according to a second burst sequence, based on the read scheduling signal.

Abstract: Disclosed are a method for manufacturing a high-density neural probe including needles having various forms and a neural probe manufactured thereby. The method, in which only a photolithography process and an etching process are used, simplifies a manufacturing process of the neural probe, minimizes changes in the characteristics of the neural probe depending on process equipment or conditions, and may thus ensure a high yield, thereby being advantageous in terms of commercialization. In addition, various forms of needles may be manufactured depending on the shape of patterns included in a mask, the height of the needles may be controlled by adjusting the size of the patterns and the gap between the patterns, and thereby, a neural probe having a plurality of needles having different heights may be manufactured.

Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.

Abstract: The disclosed technology includes an infrared-emitting quantum dot comprising a core comprising a first semiconductor material, a shell comprising a second semiconductor material, and a gradient interface between the core and the shell. The disclosed technology also includes methods of manufacturing the same.

Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.

Abstract: A memory system comprises: a memory cell array suitable for storing first data and a first parity, which is used to correct an error of the first data; and an error correcting circuit suitable for generating second data and a second parity, which includes bits obtained by correcting an error of the first parity and a bit obtained by correcting an error of a second sub-parity; wherein the error correcting circuit includes: a single error correction and double error detection (SECDED) parity generator suitable for generating a second pre-parity, which includes a first sub-parity and the second sub-parity; a syndrome decoder suitable for generating a first parity error flag and a first data error flag by decoding a syndrome; a SEC parity corrector suitable for correcting an error of the first parity based on the first parity error flag; a DED parity error detector suitable for generating a second sub-parity error flag based on an error information of the first data used to generate the second sub-parity; and a D

Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.