Abstract: An electric hydraulic brake includes a plurality of wheel brakes; a reservoir storing brake oil; a master cylinder connected to the reservoir and configured to generate hydraulic pressure with a first motor; an auxiliary actuator including a second motor and a pump unit having piston pumps linked therewith that transmits the hydraulic pressure to the wheel brakes when the master cylinder malfunctions; a hydraulic circuit that selectively transmits the hydraulic pressure to the wheel brakes, and including a front wheel hydraulic circuit and rear wheel hydraulic circuit each configured to transmit the hydraulic pressure to a pair of front wheel brakes and a pair of rear wheel brakes, respectively, and a plurality of solenoid valves; a first controller to control the first motor and the hydraulic circuit with braking input; and a second controller to control the first motor and the front wheel hydraulic circuit when the first controller malfunctions.

Abstract: Provided are: a novel pyrrolidine derivative or a pharmaceutically acceptable salt thereof; and a pharmaceutical composition containing same and having the effects of inhibiting beta-amyloid and/or tau protein aggregation, and/or breaking down beta-amyloid and/or tau protein aggregates, and/or preventing and/or treating beta-amyloid and/or tau protein-associated diseases.

Abstract: According to at least one embodiment, the present disclosure provides an electric hydraulic brake including: a plurality of wheel brakes configured to supply braking force to wheels of a vehicle; a reservoir storing brake oil; a master cylinder connected to the reservoir and configured to generate hydraulic pressure in cooperation with a motor; a hydraulic circuit configured to selectively transmit the hydraulic pressure to the plurality of wheel brakes, the hydraulic circuit including a front wheel hydraulic circuit to transmit the hydraulic pressure to a pair of front wheel brakes, a rear wheel hydraulic circuit to transmit the hydraulic pressure to a pair of rear wheel brakes, and a plurality of solenoid valves; a first controller configured to control the motor and the hydraulic circuit in accordance with braking input; and a second controller configured to control the motor and the front wheel hydraulic circuit when the first controller malfunctions.

Abstract: The present invention relates to a compound comprising an EZH2 inhibitor and an E3 ligase binder, and a pharmaceutical composition for preventing or treating EZH2-associated disease and a pharmaceutical composition for selective protein degradation containing the same as an active ingredient. Since the compound of the present invention can selectively degrade EZH2, it can be effectively used for the treatment of EZH2-related diseases and cancers, particularly, cancers in which EZH2 is overexpressed, and can be usefully used for the selective degradation of EZH2.

Abstract: This application relates to a method and apparatus for processing a new read-write-operation instruction added to an instruction set to maximize the performance of processing-in-memory (PIM). The read-write-operation instruction performs reading and writing on an operation result of the PIM by returning the operation result of the PIM to a computer system and, at the same time, writing the operation result to a destination address. An instruction processor in PIM includes a response data selector and a finite state machine to process the read-write-operation instruction. The response data selector includes a selector configured to select one of a response data signal and an operation result, and a three-phase buffer configured to allow or disallow response data. The finite state machine of the instruction processor outputs a response permission signal and a response selection signal for controlling the buffer and the selector.

Abstract: This application relates to a memory management method for maximizing processing-in-memory (PIM) performance and reducing unnecessary DRAM access time. In one aspect, when processing a PIM instruction packet, an instruction processing unit secondarily processes a request for access to a destination address at which read and write actions of an internal memory are likely to be sequentially performed. By secondarily requesting the destination address, a row address of an open page of the internal memory may match a row address to which a PIM instruction packet processing result is written back. Also, the instruction processing unit inside the PIM maintains memory write and read addresses that have previously requested. The instruction processing unit compares the address of a packet to be processed to the maintained previous memory address and informs a memory controller about the comparison result through a page closing signal.

Abstract: The present disclosure relates to a method for classifying instructions according to the number of operands required for processing-in-memory instruction processing, and a computing device applying same. Efficient instruction processing in a processing-in-memory may include identifying the number of operands required when processing an instruction queuing to be processed, interpreting the instruction queuing to be processed and processing an instruction corresponding to the identified number of required operands. When the number of required operands is 0, the instruction interpretation may interpret the instruction queuing to be processed as a WRITE instruction, and the instruction processing may execute memory writing. When the number of required operands is not 0, the instruction processing may execute memory reading in an internal memory of the processing-in-memory by the same number of times as the number of operands required in the instruction interpreted in the instruction interpretation.

Abstract: This application relates to a memory management method for maximizing processing-in-memory (PIM) performance and reducing unnecessary DRAM access time. In one aspect, when processing a PIM instruction packet, an instruction processing unit secondarily processes a request for access to a destination address at which read and write actions of an internal memory are likely to be sequentially performed. By secondarily requesting the destination address, a row address of an open page of the internal memory may match a row address to which a PIM instruction packet processing result is written back. Also, the instruction processing unit inside the PIM maintains memory write and read addresses that have previously requested. The instruction processing unit compares the address of a packet to be processed to the maintained previous memory address and informs a memory controller about the comparison result through a page closing signal.

Abstract: This application relates to a method and apparatus for processing a new read-write-operation instruction added to an instruction set to maximize the performance of processing-in-memory (PIM). The read-write-operation instruction performs reading and writing on an operation result of the PIM by returning the operation result of the PIM to a computer system and, at the same time, writing the operation result to a destination address. An instruction processor in PIM includes a response data selector and a finite state machine to process the read-write-operation instruction. The response data selector includes a selector configured to select one of a response data signal and an operation result, and a three-phase buffer configured to allow or disallow response data. The finite state machine of the instruction processor outputs a response permission signal and a response selection signal for controlling the buffer and the selector.

Abstract: According to certain embodiments of the present disclosure, an electronic device and manufacturing method are disclosed. The electronic device includes: a housing including a first face, a second face, and a side member surrounding a space defined between the first face and the second face, a support member within the housing such that a side face of the support member is oriented towards an inner wall of the side member, a circuit board mounted on one face of the support member, an electrically conductive plate mounted on a second face, and a contact member mounted on the support member to electrically couple at least a portion of the side member to the circuit board, wherein the contact member includes an end portion adjacent to the plate, and an end face of the end portion includes a width smaller than a width of another portion of the contact member.

Abstract: The present invention provides an apparatus and a method for detecting the presence of and/or determining the amount of a label-free microRNA using an atomic force microscope. The method is extremely selective and/or ultrasensitive. In particular, the present invention provides a cantilever comprising a probe that selectively binds to a double strand of DNA/RNA hybrid complex. The probe comprises a hybrid binding domain (HBD) or a variant thereof.

Abstract: Disclosed is a method of manufacturing ultrasonic sensors. The method includes forming a micropattern having concave and convex portions on an etchable substrate, filling a piezoelectric material in the concave portions of the micropattern, pressurizing the filled piezoelectric material, sintering the piezoelectric material to form preliminary piezoelectric bodies, re-sintering the preliminary piezoelectric bodies to form densely packed unit piezoelectric bodies, and forming electrode terminals at both ends of each of the unit piezoelectric bodies to produce a unit piezoelectric cell. The method enables the manufacture of high-quality ultrasonic sensors in high yield.

Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

Abstract: Provided is a glassy carbon roll-type mold manufacturing method for fine pattern formation. The method is for manufacturing a glassy carbon roll-type mold configured to form a fine pattern having a micro-nano structure on a substrate including glass or a metal. The method includes: preparing a roll precursor including a thermosetting resin material, the roll precursor having a roll shape with a circumferential surface on which a pattern corresponding to the fine pattern is formed, the roll precursor being configured to press the substrate while rotating on the substrate; and carbonizing the roll precursor.

Abstract: Provided is a glassy carbon roll-type mold manufacturing method for fine pattern formation. The method is for manufacturing a glassy carbon roll-type mold configured to form a fine pattern having a micro-nano structure on a substrate including glass or a metal. The method includes: preparing a roll precursor including a thermosetting resin material, the roll precursor having a roll shape with a circumferential surface on which a pattern corresponding to the fine pattern is formed, the roll precursor being configured to press the substrate while rotating on the substrate; and carbonizing the roll precursor.

Abstract: According to certain embodiments of the present disclosure, an electronic device and manufacturing method are disclosed. The electronic device includes: a housing including a first face, a second face, and a side member surrounding a space defined between the first face and the second face, a support member within the housing such that a side face of the support member is oriented towards an inner wall of the side member, a circuit board mounted on one face of the support member, an electrically conductive plate mounted on a second face, and a contact member mounted on the support member to electrically couple at least a portion of the side member to the circuit board, wherein the contact member includes an end portion adjacent to the plate, and an end face of the end portion includes a width smaller than a width of another portion of the contact member.

Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

Abstract: A health management system. A method of operating a home gateway for a home network connectable with at least one home device in the health management system includes receiving health information for at least one user from a health management server, generating environment control information for configuring an environment corresponding to the health information for the at least one user, and transmitting the environment control information to the at least one home device to control the at least one home device.

Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.