Abstract: Provided are ray tracing processing method and apparatus. The ray tracing processing method includes detecting, at a ray tracing processing apparatus, a leaf node with which an input ray intersects; and in response to the leaf node being detected, comparing a state of a traversal (TRV) unit and a state of an intersection test (IST) unit and determining whether to feed the ray back to the TRV unit or to transmit the ray to the IST unit.

Abstract: Provided are method and apparatuses for routing and reconfiguring rendering data, the method for routing including identifying, at a processor, a group of input data, transmitting the input data based on a routing path designated for the identified group, and updating the routing path based on a feedback signal regarding the transmitted data. The method for reconfiguring rendering units including measuring, at a processor, workloads of the rendering units used in rendering a previous frame, and reconfiguring the rendering units during rendering a current frame based on the workloads.

Abstract: Provided is a method and apparatus for measuring a performance or a progress state of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A thread progress tracking apparatus may include a selector to select at least one thread constituting an application program; a determination unit to determine, based on a predetermined criterion, whether an instruction execution scheme corresponds to a deterministic execution scheme having a regular cycle or a nondeterministic execution scheme having an irregular delay cycle with respect to each of at least one instruction constituting a corresponding thread; and a deterministic progress counter to generate a deterministic progress index with respect to an instruction that is executed by the deterministic execution scheme, excluding an instruction that is executed by the nondeterministic execution scheme.

Abstract: A cache memory system and a method of operating the cache memory system are provided. The cache memory system includes: an address buffer for receiving address bits including a cache address and a tag address from the outside or externally; a cache memory including a memory array, the cache memory outputting, from a row of the memory array which the cache address designates, a plurality of pieces of tag data and a plurality of pieces of cache data corresponding to the plurality of pieces of tag data; and a register configured to temporarily store a data set including the plurality of pieces of cache data output from the cache memory.

Abstract: A multiprocessor system and a migration method of the multiprocessor system are provided. The multiprocessor system may process dynamic data and static data of a task to be operated in another memory or another processor without converting pointers, in a distributed memory environment and in a multiprocessor environment having a local memory, so that dynamic task migration may be realized.

Abstract: A method and apparatus for managing a stack used for a tree traversal (TRV) may include a processing unit that may manage a short stack for a tree TRV, and a storage unit that may store data of the short stack. The processing unit may perform a restart of the tree TRV from an intermediate node of a tree to fill the short stack when the short stack is empty.

Abstract: A computing system, method and computer-readable medium is provided. To prevent a starvation phenomenon from occurring in a priority-based task scheduling, a plurality of tasks may be divided into a priority-based group and other groups. The groups to which the tasks belong may be changed.

Abstract: A multi-core system and a method for processing data in parallel in the multi-core system are provided. In the multi-core system, partitioning and allocating of data may be dynamically controlled based on local memory information. Thus, it is possible to increase an availability of a Central Processing Unit (CPU) and a local memory, and is possible to improve a performance of data parallel processing.

Abstract: A method for processing a three-dimensional (3D) image of a ray tracing scheme may be performed by an image processing apparatus by verifying whether local index information matching intersection point information of a ray is present within a prefetch table when intersection point information is received, and by transferring, to a shader, rendering information stored in a local memory based on the local index information, when the local index information matching the intersection point information is present.

Abstract: A graphic processing apparatus and method for processing ray tracing may include a plurality of traversal units to process traversal of a ray. A management unit of the graphics processing apparatus may distribute data of the ray processed by the graphics processing apparatus to the plurality of traversal units. Each of the plurality of traversal units may process ray traversal with respect to a subdivision of the entire space.

Abstract: An apparatus and method for ray tracing includes a traversal (TRV) unit using a tree acceleration structure (AS). The TRV unit may include a plurality of sub-pipeline units configured to perform different operations required for ray TRV using the tree AS and to operate in parallel.

Abstract: Disclosed is a device, method and computer-readable medium relocating Remote Procedure Call (RPC) data in a heterogeneous multiprocessor System-on-Chip (MPSoC). The method, for example, includes determining a memory where data is to be stored based on a use of a parameter of a function, and data access patterns of a function caller and a function callee, and storing the data in the determined memory.

Abstract: Provided are a multitasking method and apparatus. By continuously maintaining the intrinsic information of each peripheral processing unit of when a process-centered task is stopped, when a reconfigurable array stops executing the process-centered task and executes a different process-centered task, by stopping executing a control-centered task and executing a reconfiguration task, only when the reconfigurable array receives an execution request of the reconfiguration task while the reconfigurable array is performing the control-centered task, or by causing a predetermined number of processing units to execute each of a plurality of reconfiguration tasks that are to be simultaneously executed by the reconfigurable array, wherein the predetermined number of processing units is set in consideration of an expected data processing amount required for the reconfiguration task, the reconfigurable array can more quickly complete execution of multitasking.

Abstract: Provided is a method and apparatus for ray tracing. A traversal unit to process an input ray to be input among a plurality of traversal units may be determined based on age of each of the plurality of traversal units. Age of the determined traversal unit may be determined based on age of each of rays that are processed by the traversal unit.

Abstract: An apparatus and method for detecting an error occurring when an application program is executed in a computer environment is provided. The error detection apparatus may measure a deterministic progress index (DPI) and a program counter (PC) value when an instruction is executed, set, as a verification set, a DPI and a PC value measured when the instruction is executed without causing an error, set, as a measurement set, the DPI and the PC value measured when an instruction is executed, and detect a runtime error of the instruction by comparing the measurement set to the verification set.

Abstract: Provided is an apparatus and method for managing power based on data. The apparatus may include a code segment searching unit configured to search for at least one code segment in which a power type is inserted, a block determining unit configured to determine at least one block based on the at least one found code segment, and a power mode control unit configured to control the at least one determined block to operate in a power mode corresponding to the power type.

Abstract: An apparatus and method for traversing a hierarchical acceleration structure may determine whether a current traversal node is a leaf node, may calculate a first distance from the current traversal node to a pop level and a second distance from a root node to the pop level when the current traversal node is the leaf node, and may determine a hierarchical traversal restarting position by comparing the first distance and the second distance.

Abstract: A method and apparatus for detecting errors in an application software of an embedded system are provided. The method of detecting errors in an application software includes determining a development language of the application software and an operating system on which the application software is executed; replacing an error detection syntax inserted in order to examine an error in a predetermined function of the application software, with an error detection syntax according to the result of the determination; and performing exception handling for an error occurring in the function according to the result of the replacement, and logging error information according to the exception handling. According to the method and apparatus, an error can be automatically detected and logged irrespective of a development language and an operating system.

Abstract: A dynamic task management system and method for data parallel processing on a multi-core system are provided. The dynamic task management system may generate a registration signal for a task to be parallel processed, may generate a dynamic management signal used to dynamically manage at least one task, in response to the generated registration signal, and may control the at least one task to be created or cancelled in at least one core in response to the generated dynamic management signal.

Abstract: A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.