Abstract: A display device includes: a screen saver operable to cause an image to be displayed with a lowered luminance in a screen save mode by lowering a scale factor from a first value based on the image being displayed as a still image longer than a reference time; and an overcurrent protection circuit operable to detect an overcurrent and cause a power of the display device to be turned off based on a predetermined current value that is reduced according to the scale factor and comparison between the predetermined current value and a driving current supplied provided to a display panel in which the image is displayed.

Abstract: A display device includes a display panel, a first memory, and a degradation compensator. The first memory device stores stress data including degradation values representing a degradation degree of each of the blocks in the display panel. The degradation compensator loads the stress data from the first memory device, updates the stress data based on current input data and a maximum degradation value, updates the maximum degradation value based on degradation values included in the updated stress data, and generate compensated data by compensating for the current input data based on the updated stress data. The degradation compensator determines whether a first degradation value included in the stress data is normal by comparing the first degradation value with the maximum degradation value, and updates the first degradation value based on at least one adjacent degradation value adjacent to the first degradation value, when the first degradation value is abnormal.

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Abstract: A display device includes a display panel, a first memory, and a degradation compensator. The first memory device stores stress data including degradation values representing a degradation degree of each of the blocks in the display panel. The degradation compensator loads the stress data from the first memory device, updates the stress data based on current input data and a maximum degradation value, updates the maximum degradation value based on degradation values included in the updated stress data, and generate compensated data by compensating for the current input data based on the updated stress data. The degradation compensator determines whether a first degradation value included in the stress data is normal by comparing the first degradation value with the maximum degradation value, and updates the first degradation value based on at least one adjacent degradation value adjacent to the first degradation value, when the first degradation value is abnormal.

Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

Abstract: The display device includes a first pixel connected to a first scan line and a first data line, a second pixel connected to a second scan line and the first data line, a scan driver configured to supply a scan signal to the first scan line and the second scan line, and a data driver connected to the first data line. The data driver provides a first data signal to the first pixel when the scan signal is applied to the first scan line, the data driver provides a second data signal to the second pixel when the scan signal is applied to the second scan line, and a length of a first period in which the first data signal is provided is different from a length of a second period in which the second data signal is provided.

Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Abstract: A timing controller includes a data grouping part that generates a plurality of grayscale groups based on input image data, each grayscale group including n×m grayscales, a grayscale classifying part that generates a plurality of grayscale patterns respectively corresponding to the grayscale groups, a grayscale in the grayscale groups being classified in the grayscale patterns as a first grayscale if the grayscale is higher than a first reference grayscale or as a second grayscale if the grayscale is lower than a second reference grayscale, a pattern comparing part that compares each grayscale pattern with a first pattern including the n×m first and second grayscales, a pattern counter that counts a number of patterns of the grayscale patterns that are substantially the same as the first pattern, and a driving mode changing part that changes a driving mode of a display panel when the number is greater than a reference number.

Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

Abstract: A gate driver includes a first shift-register including a plurality of odd-numbered stages which outputs a plurality of odd-numbered original gate signals having a pre-charge pulse and a main-charge pulse in synchronization with a first gate clock signal, a second shift-register comprising a plurality of even-numbered stages which outputs a plurality of even-numbered original gate signals having a pre-charge pulse and a main-charge pulse in synchronization with a second gate clock signal, a first inverter configured to output a first inversion pre-charge control signal having a phase opposite to a phase of a first pre-charge control signal, and a second inverter configured to output a second inversion pre-charge control signal having a phase opposite to a phase of a second pre-charge control signal.

Abstract: A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

Abstract: The present disclosure relates to a display device including: a substrate having a rounded corner; a plurality of pixels disposed on the substrate; and a light blocking member disposed on a corner of the substrate and overlapping at least part of a first pixel of the plurality of pixels, the first pixel disposed at the rounded corner, wherein the first pixel is configured to generate a lower luminance, the lower luminance referring to a luminance lower than a normal luminance.

Abstract: A display device includes: a data mapping portion including a memory having addresses corresponding to locations of pixels and which maps an input image signal to a corresponding address; a pattern detector which detects an image quality deterioration pattern in pattern detection areas from the mapped input image signal; a pattern counting portion which generates pattern information by counting the image quality deterioration pattern; a data analyzing portion which divides the input image signal for each frame and selects a representative value of an input image signal of a frame; and a controller which generates an image data signal based on a first inversion method or a second inversion method by determining whether the counted number of the image quality deterioration pattern exceeds a threshold value based on the pattern information, and determines a level of a common voltage corresponding to the representative value.

Abstract: A display apparatus includes a display panel comprising a plurality of gate lines and a plurality of data lines, a gate driver circuit configured to generate a plurality of gate signals sequentially applied to the gate lines, and a timing controller configured to generate a reference control signal, the reference control signal adjusting at least one of a pulse-width and a phase of a predetermined gate signal among the gate signals.

Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.