Abstract: An apparatus for detecting a lock failure and correcting a duty cycle includes a lock failure detector configured to determine whether a first internal clock signal is locked to a second internal clock signal and to output a lock failure signal in response thereto, a duty cycle correction unit configured to correct a duty cycle of an external clock signal responsive to the lock failure signal and to output the duty-cycle-corrected external clock signal as the first internal clock signal, and a delay unit configured to generate the second internal clock signal by delaying the first internal clock signal.

Abstract: The PLL includes a selection signal generator configured to output a selection signal varying in response to a first clock signal, and a first dividing circuit configured to divide an externally input reference clock signal by a division ratio and output a first division signal. The first dividing circuit selects one of a plurality of edges of the reference clock signal applied for at least one cycle of the first division signal in response to the selection signal, and synchronizes and generates the first division signal on the basis of the selected edge of the reference clock signal. A second dividing circuit is configured to receive an output clock signal, divide the output clock signal by a division ratio, and output a second division signal.

Abstract: In a decision feedback equalization (DFE) input buffer, timing and voltage errors, such as those caused by inter-symbol interference (ISI), are fully compensated. A variable equalizing coefficient is applied that accommodates, and compensates for, a range of timing errors TE or voltage errors VE that may be generated over a range of operating conditions. In this manner, accurate compensation is achieved, allowing for greater signal reliability and higher inter-circuit transfer rates. A decision feedback equalization (DFE) input buffer includes an equalizer that amplifies a difference in voltage level between an input signal and an oversampled signal in response to a variable equalizing control signal, the equalizer generating an amplified output signal. A sampling unit samples the amplified output signal in response to a sampling clock signal to generate the oversampled signal.

Abstract: Integrated circuit memory devices include an internal command generator and a memory control circuit responsive to an internal command generated by the internal command generator. The internal command generator is configured to generate an internal command in response to a combination of an independent command and at least one dependent command received in sequence by the memory device. For example, the internal command generator may be configured to require the independent command to follow the at least one dependent command in the sequence when generating the internal command from the combination of the independent and dependent commands. Alternatively, the internal command generator may be configured to require the independent command to precede the at least one dependent command in the sequence before generating the internal command from the combination of the independent and dependent commands.

Abstract: A data amplifying circuit for an output driver has a swing level that is controllable according to an operation mode. The data amplifying circuit includes a mode responding circuit supplying an additional source current to a source node of an amplifying circuit in response to a mode selection signal. The mode responding circuit controls the supply of the additional source current in accordance with an operation mode. Another data amplifying circuit of a semiconductor device, according to the invention, includes a small-swing amplifier and a full-swing amplifier. The small-swing amplifier causes a swing level of the output signal to be relatively smaller, while the full-swing amplifier causes the output signal swing level be relatively larger. The small-swing and full-swing amplifiers are alternatively enabled in response to the mode selection signal.

Abstract: A sense amplifier flip flop including a differential input portion, a differential amplifying portion including a first inverter and a second inverter, and a bias voltage generating portion. The bias voltage generating portion is configured to generate body voltages for transistors of the first inverter and the second inverter so that an offset between electric currents flowing through the differential input portion can be adjusted.

Abstract: An On Die Termination (ODT) circuit for performing an ODT operation. The ODT circuit includes a resistor having a first end to receive an ODT enable signal; and a switch unit coupled to a second end of the resistor. The ODT operation is performed in response to the ODT enable signal passing through the resistor.

Abstract: A charge pump circuit may include a cross-coupled load unit and a bias determination unit. The cross-coupled load unit may receive first and second input signals applied with mutually opposite phases to obtain a charge pumping. The cross-coupled load unit may have first and second output terminals that may be connected with transistors in a cascade connection structure. The bias determination unit may have a current mirror structure, and independently determine biases of a transistor among the cascade structure connected transistors in response to voltages of the first and second output terminals.

Abstract: A data amplifying circuit for an output driver has a swing level that is controllable according to an operation mode. The data amplifying circuit includes a mode responding circuit supplying an additional source current to a source node of an amplifying circuit in response to a mode selection signal. The mode responding circuit controls the supply of the additional source current in accordance with an operation mode. Another data amplifying circuit of a semiconductor device, according to the invention, includes a small-swing amplifier and a full-swing amplifier. The small-swing amplifier causes a swing level of the output signal to be relatively smaller, while the full-swing amplifier causes the output signal swing level be relatively larger. The small-swing and full-swing amplifiers are alternatively enabled in response to the mode selection signal.

Abstract: A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluation signal pair corresponding to an input single pair to the first output terminal pair. The second latch latches the evaluation signal pair and outputs the evaluation signal pair to a second output terminal pair. The floating reduction unit is controlled by signals of the first output terminal pair and is operationally connected between current passing nodes of the first latch to prevent the first output terminal pair from floating. The input signal applying unit is disposed between the current passing nodes and a ground terminal, and receives the input signal pair. The ground switch is disposed between the input signal applying unit and the ground terminal, and is controlled by the clock signal.

Abstract: Example embodiments relate to a semiconductor memory module and memory system, and a method of communicating therein. According to an example embodiment, a semiconductor memory system may include a memory controller, M interconnected memory elements, and/or N data buses, where N is a natural number and M is a divisor of N. The N data buses may connect the M memory elements to the memory controller. Each memory element may use N/M of the N number of data buses.

Abstract: An apparatus for detecting a lock failure and correcting a duty cycle includes a lock failure detector configured to determine whether a first internal clock signal is locked to a second internal clock signal and to output a lock failure signal in response thereto, a duty cycle correction unit configured to correct a duty cycle of an external clock signal responsive to the lock failure signal and to output the duty-cycle-corrected external clock signal as the first internal clock signal, and a delay unit configured to generate the second internal clock signal by delaying the first internal clock signal.

Abstract: An output driver for enhancing initial output data using timing includes a selection signal generation unit for generating a selection signal, a reference data generation unit for generating reference data, and a selection unit. The selection signal is activated at the transition point of the input data, generated after being maintained in a same logic state during a number of bit periods that is equal to or greater than a predetermined duration number. The reference data is delayed from the input data by a delay time shorter than one bit period. The selection unit is driven to transition the logic state of the output data depending on the transition of the logic state of any one of the input data and the reference data in response to the selection signal.

Abstract: Provided are a differential amplifier circuit and a method of generating a bias voltage in a differential amplifier circuit. The differential amplifier circuit is turned on or turned off in response to an input voltage and includes a differential amplifier and a bias circuit. The bias circuit provides a first bias voltage to a gate of a pull-down transistor included in the differential amplifier when the differential amplifier is turned on and provides second bias voltage which is lower than the first bias voltage to the gate of the pull-down transistor when the differential amplifier is turned off.

Abstract: A duty detector may include a first amplifier and/or an integrator. The first amplifier may be configured to receive a first signal and a complementary first signal, differential-amplify the first signal and the complementary first signal, and/or output the differential-amplified first signal to an output terminal and the differential-amplified complementary first signal to a complementary output terminal. The integrator may be connected to the output terminal and the complementary output terminal of the first amplifier, configured to integrate the differential-amplified first signal and the differential-amplified complementary first signal, and/or configured to output a duty detection signal.

Abstract: A process-insensitive self-biasing PLL circuit and self-biasing method thereof prevent deterioration of loop stability even when there is a fabrication process variation. The self-biasing PLL circuit includes a phase frequency detector, a main charge pump circuit, an auxiliary charge pump circuit, a first operational amplifier, a second operational amplifier, a voltage-controlled oscillator, a divider, and a bias circuit. In the self-biasing PLL circuit, the first operational amplifier amplifies the voltage of a loop filter capacitor and the second operational amplifier serving as a regulator amplifies the output voltage of the first operational amplifier. The output voltage of the second operational amplifier is used as a control voltage of the voltage-controlled oscillator.

Abstract: A phase locked loop includes a phase difference detector for detecting a phase difference between an input clock signal and an output clock signal to generate an up signal and a down signal; a charge pump for raising a level of a control signal by supplying a supply current in response to the up signal, for lowering a level of the control signal by discharging a discharge current in response to the down signal, and for adjusting the supply current in response to a first control voltage and by discharge current in response to a second control voltage in a locked state; a compensator for generating the first and second control voltages corresponding to difference between the up signal and the down signal in the locked state; and a voltage controlled oscillator for varying a frequency of the output clock signal in response to the control signal.

Abstract: A sense amplifier-based flip-flop includes a first latch, a second latch, a floating reduction unit, an input signal applying unit, a ground switch and a delay reduction unit. The first latch outputs a signal to a first output terminal pair, and outputs an evaluation signal pair corresponding to an input single pair to the first output terminal pair. The second latch latches the evaluation signal pair and outputs the evaluation signal pair to a second output terminal pair. The floating reduction unit is controlled by signals of the first output terminal pair and is operationally connected between current passing nodes of the first latch to prevent the first output terminal pair from floating. The input signal applying unit is disposed between the current passing nodes and a ground terminal, and receives the input signal pair. The ground switch is disposed between the input signal applying unit and the ground terminal, and is controlled by the clock signal.

Abstract: An output driver and an I/O apparatus including the output driver are disclosed. The output driver includes a driving unit having a first type transistor and a second type transistor connected in series, the driving unit amplifying an input signal applied to the gates of the first type transistor and the second type transistor and outputting the amplified signal to a node between the series connected first type transistor and second type transistor, a first source peaking unit connected between the first type transistor and a first voltage source and having a first impedance that varies in accordance with the frequency of the input signal, and a second source peaking unit connected between the second type transistor and a second voltage source and having a second impedance that varies in accordance with the frequency of the input signal.

Abstract: A reference voltage generator generates a reference voltage that is less dependent on temperature and can adjust the dependence of the reference voltage on temperature and the reference voltage at the same time independently of each other. The reference voltage generator including a preliminary reference voltage generation unit which generates a preliminary reference voltage which is inversely proportional to temperature and a reference voltage generation unit which generates a reference voltage by dividing the preliminary reference voltage. The reference voltage generation unit includes: at least one resistor which is connected between the preliminary reference voltage and the reference voltage; at least one transistor which is connected between the reference voltage and an internal node; and at least one second resistor which is connected between the internal node and a ground. The preliminary reference voltage or a power supply voltage is applied to at least one gate of the transistor.