Abstract: The present invention relates to a method and device for determining the presence or absence of a target analyte in a sample. The present invention may analyze the target analyte without false results, especially false positive results by using a fitting accuracy of a nonlinear function to a data set as a direct indicator for target analyte analysis.

Abstract: A device for multi-receive multi-subscriber identity module (SIM) includes an input buffer configured to provide samples of a baseband signal, a rake receiver including plural fingers and configured to generate a series of symbols from the samples, and a controller configured to assign the fingers to a single SIM in a multi-standby mode and respectively assign two or more finger groups divided from the fingers to two or more SIMs in a multi-receive mode.

Abstract: A multi-subscriber identification module (SIM) device is provided, and includes first and second SIMs, first and second radio frequency (RF) resources, and a baseband processor. The first and second SIMs are for using first and second services of first and second networks respectively. The first RF resource supports a non-limiting channel configuration use in accordance with a radio resource control (RRC) protocol. The second RF resource supports a limiting channel configuration use in accordance with the RRC protocol. The baseband processor, in a dual radio (DR) mode, configures one of the first and second SIMs as a main SIM based on information on the first and second networks, allots the first RF resource to the main SIM, configures the other one as a sub-SIM, and allots the second RF resource to the sub-SIM.

Abstract: A multi-subscriber identification module (SIM) device includes: a first SIM configured to use a service of a first network; a second SIM configured to use a service of a second network; a first RF resource configured to support use of non-limited channel configuration according to a radio resource control (RRC) protocol; a second RF resource configured to support use of limited channel configuration according to the RRC protocol; and a baseband processor configured to selectively assign any one of the first RF resource and the second RF resource to the first SIM and the second SIM, based on information regarding the first network and the second network.

Abstract: The present disclosure relates to an isolated anti-FcRn antibody, which is an antibody binding to FcRn (stands for neonatal Fc receptor, also called FcRP, FcRB or Brambell receptor) that is a receptor with a high affinity for IgG or a fragment thereof, a method of preparing thereof, a composition for treating autoimmune disease, which comprises the antibody, and a method of treating and diagnosing autoimmune diseases using the antibody. The FcRn-specific antibody according to the present disclosure binds to FcRn non-competitively with IgG to reduce serum pathogenic auto-antibody levels, and thus can be used for the treatment of autoimmune diseases.

Abstract: The present disclosure relates to an isolated anti-FcRn antibody, which is an antibody binding to FcRn (stands for neonatal Fc receptor, also called FcRP, FcRB or Brambell receptor) that is a receptor with a high affinity for IgG or a fragment thereof, a method of preparing thereof, a composition for treating autoimmune disease, which comprises the antibody, and a method of treating and diagnosing autoimmune diseases using the antibody. The FcRn-specific antibody according to the present disclosure binds to FcRn non-competitively with IgG to reduce serum pathogenic auto-antibody levels, and thus can be used for the treatment of autoimmune diseases.

Abstract: The present disclosure relates to an isolated anti-FcRn antibody, which is an antibody binding to FcRn (stands for neonatal Fc receptor, also called FcRP, FcRB or Brambell receptor) that is a receptor with a high affinity for IgG or a fragment thereof, a method of preparing thereof, a composition for treating autoimmune disease, which comprises the antibody, and a method of treating and diagnosing autoimmune diseases using the antibody. The FcRn-specific antibody according to the present disclosure binds to FcRn non-competitively with IgG to reduce serum pathogenic auto-antibody levels, and thus can be used for the treatment of autoimmune diseases.

Abstract: The present disclosure relates to an isolated anti-FcRn antibody, which is an antibody binding to FcRn (stands for neonatal Fc receptor, also called FcRP, FcRB or Brambell receptor) that is a receptor with a high affinity for IgG or a fragment thereof, a method of preparing thereof, a composition for treating autoimmune disease, which comprises the antibody, and a method of treating and diagnosing autoimmune diseases using the antibody. The FcRn-specific antibody according to the present disclosure binds to FcRn non-competitively with IgG to reduce serum pathogenic auto-antibody levels, and thus can be used for the treatment of autoimmune diseases.

Abstract: The present invention relates to a human antibody specific for FcRn that is a receptor with a high affinity for IgG, a production method thereof, a composition for treating autoimmune disease, which comprises the antibody, and a method of treating and diagnosing autoimmune disease using the same. The FcRn-specific antibody according to the present invention can bind to FcRn non-competitively with IgG or the like to reduce serum auto-antibody levels, and thus can be used for the treatment of autoimmune diseases.

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.

Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.

Abstract: A space registration system includes a display apparatus, an image sensor, a processor, and a plane mirror. The display apparatus has an inherent display coordinate system which defines a coordinate of the virtual space. The image sensor has an inherent sensor coordinate system which defines a coordinate of the real space. The processor analogizes a transformation equation of the sensor coordinate system and the display coordinate system by means of symmetry of an incidence angle and a reflection angle of light with respect to the mirror surface, compares a coordinate of the reflection image with respect to the display coordinate system with a known coordinate of the reflection image with respect to the sensor coordinate system, and adjusts the transformation equation of the sensor coordinate system and the display coordinate system.

Abstract: A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.

Abstract: The present disclosure relates to an isolated anti-FcRn antibody, which is an antibody binding to FcRn (stands for neonatal Fc receptor, also called FcRP, FcRB or Brambell receptor) that is a receptor with a high affinity for IgG or a fragment thereof, a method of preparing thereof, a composition for treating autoimmune disease, which comprises the antibody, and a method of treating and diagnosing autoimmune diseases using the antibody. The FcRn-specific antibody according to the present disclosure binds to FcRn non-competitively with IgG to reduce serum pathogenic auto-antibody levels, and thus can be used for the treatment of autoimmune diseases.

Abstract: The present disclosure relates to an isolated anti-FcRn antibody, which is an antibody binding to FcRn (stands for neonatal Fc receptor, also called FcRP, FcRB or Brambell receptor) that is a receptor with a high affinity for IgG or a fragment thereof, a method of preparing thereof, a composition for treating autoimmune disease, which comprises the antibody, and a method of treating and diagnosing autoimmune diseases using the antibody. The FcRn-specific antibody according to the present disclosure binds to FcRn non-competitively with IgG to reduce serum pathogenic auto-antibody levels, and thus can be used for the treatment of autoimmune diseases.

Abstract: A method of manufacturing a semiconductor chip from a wafer having a test architecture includes forming a plurality of dies on a wafer, each of the plurality of dies including a semiconductor device, forming at least two common pads commonly coupled to the dies, the at least two common pads being formed in a scribe lane, the scribe lane distinguishing the dies with respect to each other, and simultaneously testing the semiconductor devices at a wafer level, using the at least two common pads.

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an error correction circuit and a first path selection circuit. The memory cell array includes a plurality of bank arrays. The control logic circuit controls access to the memory cell array and generates a density mode signal based on a command. The first path selection circuit selectively provides write data to the error correction circuit.

Abstract: A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address.

Abstract: The present invention relates to a cart with easy accommodation of a handle by a spring, comprising: a loading plate in which articles are loaded at the upper portion, a cut groove is vertically penetrated to be formed at the front end, the front end is opened at the lower portion so as to be horizontally penetrated to the back end, and a space part is formed to communicate with the cut groove; driving wheels provided at the lower part of the loading plate; a cover to be coupled to the lower part of the space part; a handle member accommodated in the space part so as to be moved to the front end of the loading plate, and rotated toward the cut groove so as to be exposed to the upper part of the loading plate; a stopper formed at the cut groove side in the space portion and preventing the separation of the handle member; and a spring unit comprising a fixture provided in the back of the space part, a rotation shaft provided at the fixture, and a spring wound to the rotation shaft and of which an end is connect

Abstract: A space registration system includes a display apparatus, an image sensor, a processor, and a plane mirror. The display apparatus has an inherent display coordinate system which defines a coordinate of the virtual space. The image sensor has an inherent sensor coordinate system which defines a coordinate of the real space. The processor analogizes a transformation equation of the sensor coordinate system and the display coordinate system by means of symmetry of an incidence angle and a reflection angle of light with respect to the mirror surface, compares a coordinate of the reflection image with respect to the display coordinate system with a known coordinate of the reflection image with respect to the sensor coordinate system, and adjusts the transformation equation of the sensor coordinate system and the display coordinate system.