Abstract: A method for radio resource allocation in a wireless communication system comprises the steps of: receiving a channel indicator for indicating the frequency band used by a neighboring base station from a gateway that controls at least one base station that accesses the core network of a wireless communication system via an IP network; assigning to an available channel list a frequency band remaining after the frequency band indicated by said channel indicator is excluded from the entire frequency band, wherein said entire frequency band is divided into a plurality of frequency bands, and said channel indicator comprises indices that indicate respective frequency bands; and selecting, as one's own channel, at least one frequency band from said available channel list.

Abstract: An apparatus and method for receiving data when an HS-SCCH is not used in a mobile communication system are provided. In the apparatus and method, retransmission data is received, parameters including information about initial transmission data are acquired from the retransmission data, the initial transmission data is retrieved from a second-rate dematching input buffer based on the information about the initial transmission data, second-rate dematching is performed on the initial transmission data and the retransmission data, and first output data is generated by soft-combining the second rate-dematched initial transmission data with the second rate-dematched retransmission data. Accordingly, memory usage can be reduced.

Abstract: A data transmission method for a high-speed packet access system includes: sending, by a user equipment, packet data containing scheduling information having size information of a packet buffer through an uplink channel to a base station, and sending quality indicator information and acknowledgement information through another uplink channel to the base station; determining, by the base station, the value of a turbo mode flag by comparing amounts of data stored in the packet buffer of the user equipment and a packet buffer of the base station respectively with preset thresholds; and deactivating, by the user equipment when the turbo mode flag of an order message contained in received control data, packet data reception and control data transmission, and redirecting transmit power of a specified transmitter to a packet data transmitter to increase transmit power of the packet data transmitter for faster packet data upload.

Abstract: An apparatus and method for simultaneous transmission scheduling in a multi-hop cellular system are provided, in which a base station presets simultaneous transmission relay station set information and transmits the simultaneous transmission relay station set information to relay stations managed by the base station, and an relay station receives the simultaneous transmission relay station set information from the base station, determines, upon receipt of a data frame from the base station, a state of the relay station preset in relation to a receiving relay station for the data frame by comparing an ID of the receiving relay station included in the data frame with the simultaneous transmission relay station set information, and operates according to the preset state.

Abstract: A method for receiving multicast service data by a terminal in a communication system. The method includes receiving a pilot from a base station, measuring channel state information using the received pilot, and transmitting the channel state information to the base station; receiving a frame from the base station, and determining whether there is an error in the received frame; when no error has occurred in the received frame, determining whether the number of frames consecutively received without error is greater than or equal to a predetermined number; and when the number of frames consecutively received without error is greater than or equal to the predetermined number, transitioning to a non-feedback state where the terminal transmits no channel state information to the base station. The frame includes multicast service data.

Abstract: A word line driving circuit includes an address decoding signal generating unit and a word line voltage supply unit. The address decoding signal generating unit includes inverter chain receiving and delaying a first address decoding signal and outputting the delayed first address decoding signal. The word line voltage supply unit includes a pull-up driver that supplies the delayed first address signal to a selected word line in response to a second address decoding signal. The inverter chain includes an NMOS transistor outputting the delayed first address signal and a source terminal of the NMOS transistor receives a set voltage that is higher than a ground voltage and lower than a high voltage.

Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a plurality of comparators receiving output data signals from each of a plurality of sub-array blocks, comparing the output data signals from each of the plurality of sub-array blocks and outputting a plurality of comparison result signals and a test circuit receiving the plurality of comparison result signals from the plurality of comparators, respectively, the test circuit configured to selectively output one of a given one of the plurality of comparison result signals on a given data input/output pad and a given signal obtained by performing a logical operation on at least two of the plurality of comparison result signals on the given data input/output pad in response to a select signal.

Abstract: According to some of the inventive concepts, a semiconductor memory device may include a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

Abstract: Provided are a DLL circuit having a coarse lock time adaptive to a frequency band of an external clock signal and a semiconductor memory device having the DLL circuit. The DLL circuit includes a delay circuit, a replica circuit, and a phase detector. The phase detector generates a first comparison signal used by the delay circuit to delay an external clock signal in units of a first cell delay time or a second comparison signal used by the delay circuit to delay the external clock signal in units of a second cell delay time. The DLL circuit delays the external clock signal by the cell delay time adaptive to the frequency band of the external clock signal, and thus can perform an accurate and rapid coarse lock operation for the entire frequency band.

Abstract: An insert for a carrier board of a test handler is disclosed. The insert pocket having hooks is detachably coupled to the insert body. The insert body can be reused. The latch apparatus is installed to the insert pocket, so that the damaged latch apparatus can be easily replaced. The insert has a plurality of holes in the bottom of the loading part thereof, to expose the leads of the semiconductor devices through the holes in the lower direction. Thus, the insert can load semiconductor devices regardless of the sizes of the semiconductor devices.

Abstract: A navigation system for an acetabular cup, which guides an insertion orientation of the acetabular cup inserted into a pelvis during a total hip replacement surgery, includes: a pelvis position tracer which includes probes in contact with three particular points of the pelvis placed on an anterior pelvic plane and a first reference mechanism disposed to indicate a specific reference plane when the probes come in contact with the particular points; and a pelvis position indicator which is fixed to the pelvis, and includes a second reference mechanism that is adjustable to indicate a plane parallel to the specific reference plane indicated by the first reference mechanism, or to indicate a plane perpendicular thereto, or to indicate the both planes.

Abstract: An apparatus and method for receiving data when an HS-SCCH is not used in a mobile communication system are provided. In the apparatus and method, retransmission data is received, parameters including information about initial transmission data are acquired from the retransmission data, the initial transmission data is retrieved from a second-rate dematching input buffer based on the information about the initial transmission data, second-rate dematching is performed on the initial transmission data and the retransmission data, and first output data is generated by soft-combining the second rate-dematched initial transmission data with the second rate-dematched retransmission data. Accordingly, memory usage can be reduced.

Abstract: A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.

Abstract: An insert for a carrier board of a test handler is disclosed. In a first aspect, the latch block applying to the insert is detachably coupled to the insert body. The latch block can be reused, and thus this reduces wastage of resources and eliminates the insert replacement fee. In a second aspect, the insert pocket having hooks is detachably coupled to the insert body. The insert body can be reused. The latch unit is installed to the insert pocket, so that the damaged latch unit can be easily replaced. The insert forms a plurality of holes in the bottom of the loading part thereof, to expose the leads of the semiconductor devices through the holes downwardly. Thus, the insert can load semiconductor devices regardless of the dimensions of the semiconductor devices.

Abstract: A method for receiving multicast service data by a terminal in a communication system. The method includes receiving a pilot from a base station, measuring channel state information using the received pilot, and transmitting the channel state information to the base station; receiving a frame from the base station, and determining whether there is an error in the received frame; when no error has occurred in the received frame, determining whether the number of frames consecutively received without error is greater than or equal to a predetermined number; and when the number of frames consecutively received without error is greater than or equal to the predetermined number, transitioning to a non-feedback state where the terminal transmits no channel state information to the base station. The frame includes multicast service data.

Abstract: A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.

Abstract: Provided are a DLL circuit having a coarse lock time adaptive to a frequency band of an external clock signal and a semiconductor memory device having the DLL circuit. The DLL circuit includes a delay circuit, a replica circuit, and a phase detector. The phase detector generates a first comparison signal used by the delay circuit to delay an external clock signal in units of a first cell delay time or a second comparison signal used by the delay circuit to delay the external clock signal in units of a second cell delay time. The DLL circuit delays the external clock signal by the cell delay time adaptive to the frequency band of the external clock signal, and thus can perform an accurate and rapid coarse lock operation for the entire frequency band.

Abstract: A semiconductor memory device and method thereof are provided. The example semiconductor memory device may include a plurality of comparators receiving output data signals from each of a plurality of sub-array blocks, comparing the output data signals from each of the plurality of sub-array blocks and outputting a plurality of comparison result signals and a test circuit receiving the plurality of comparison result signals from the plurality of comparators, respectively, the test circuit configured to selectively output one of a given one of the plurality of comparison result signals on a given data input/output pad and a given signal obtained by performing a logical operation on at least two of the plurality of comparison result signals on the given data input/output pad in response to a select signal.

Abstract: An apparatus is invented for implementing adaptive routing in packet switched networks. The hardware structure of the apparatus is based on the AntNet, which is an adaptive routing algorithm for selecting an optimized network route using a mobile agent that simulates an ant. The AntNet-based hardware structure can be applied to a system-on-chip system. The original AntNet algorithm is adapted for hardware implementation. Performance of the modified algorithm of the invention was verified by comparing the modified algorithm with the original AntNet algorithm in a virtual network structure. The hardware structure of the invention is effective for AntNet-based routing.

Abstract: A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe (CAS) latency signal, and a second CAS latency signal. The front stage circuit compares the phase of an external clock signal and the phase of a feedback signal and delays the external clock signal based on the phase difference between the external clock signal and the feedback signal to generate a first clock signal. The back stage circuit executes interpolation and duty-cycle correction on the first clock signal.