Abstract: A space registration system includes a display apparatus, an image sensor, a processor, and a plane mirror. The display apparatus has an inherent display coordinate system which defines a coordinate of the virtual space. The image sensor has an inherent sensor coordinate system which defines a coordinate of the real space. The processor analogizes a transformation equation of the sensor coordinate system and the display coordinate system by means of symmetry of an incidence angle and a reflection angle of light with respect to the mirror surface, compares a coordinate of the reflection image with respect to the display coordinate system with a known coordinate of the reflection image with respect to the sensor coordinate system, and adjusts the transformation equation of the sensor coordinate system and the display coordinate system.

Abstract: The present invention relates to a cart with easy accommodation of a handle by a spring, comprising: a loading plate in which articles are loaded at the upper portion, a cut groove is vertically penetrated to be formed at the front end, the front end is opened at the lower portion so as to be horizontally penetrated to the back end, and a space part is formed to communicate with the cut groove; driving wheels provided at the lower part of the loading plate; a cover to be coupled to the lower part of the space part; a handle member accommodated in the space part so as to be moved to the front end of the loading plate, and rotated toward the cut groove so as to be exposed to the upper part of the loading plate; a stopper formed at the cut groove side in the space portion and preventing the separation of the handle member; and a spring unit comprising a fixture provided in the back of the space part, a rotation shaft provided at the fixture, and a spring wound to the rotation shaft and of which an end is connect

Abstract: The present invention relates to a human antibody specific for FcRn that is a receptor with a high affinity for IgG, a production method thereof, a composition for treating autoimmune disease, which comprises the antibody, and a method of treating and diagnosing autoimmune disease using the same. The FcRn-specific antibody according to the present invention can bind to FcRn non-competitively with IgG or the like to reduce serum auto-antibody levels, and thus can be used for the treatment of autoimmune diseases.

Abstract: A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address.

Abstract: Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle.

Abstract: A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.

Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

Abstract: A data transmission method for a high-speed packet access system includes: sending, by a user equipment, packet data containing scheduling information having size information of a packet buffer through an uplink channel to a base station, and sending quality indicator information and acknowledgement information through another uplink channel to the base station; determining, by the base station, the value of a turbo mode flag by comparing amounts of data stored in the packet buffer of the user equipment and a packet buffer of the base station respectively with preset thresholds; and deactivating, by the user equipment when the turbo mode flag of an order message contained in received control data, packet data reception and control data transmission, and redirecting transmit power of a specified transmitter to a packet data transmitter to increase transmit power of the packet data transmitter for faster packet data upload.

Abstract: A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.

Abstract: A method for radio resource allocation in a wireless communication system comprises the steps of: receiving a channel indicator for indicating the frequency band used by a neighboring base station from a gateway that controls at least one base station that accesses the core network of a wireless communication system via an IP network; assigning to an available channel list a frequency band remaining after the frequency band indicated by said channel indicator is excluded from the entire frequency band, wherein said entire frequency band is divided into a plurality of frequency bands, and said channel indicator comprises indices that indicate respective frequency bands; and selecting, as one's own channel, at least one frequency band from said available channel list.

Abstract: A handover method according to one embodiment of the present invention comprises the steps of receiving the result of a cell measurement for a neighbor cell from a terminal, judging whether the neighbor cell is a near neighbor cell in accordance with the result of the cell measurement, calculating the ratio of the near neighbor cell to the total neighbor cells, and transmitting a command for a handover to a target cell to the terminal if the ratio exceeds the handover threshold value. The handover method of the present invention reduces interference between cells, and efficiently uses radio resources.

Abstract: An insert for a carrier board of a test handler is disclosed. The insert pocket having hooks is detachably coupled to the insert body. The insert body can be reused. The latch apparatus is installed to the insert pocket, so that the damaged latch apparatus can be easily replaced. The insert has a plurality of holes in the bottom of the loading part thereof, to expose the leads of the semiconductor devices through the holes in the lower direction. Thus, the insert can load semiconductor devices regardless of the sizes of the semiconductor devices.

Abstract: An apparatus and method for simultaneous transmission scheduling in a multi-hop cellular system are provided, in which a base station presets simultaneous transmission relay station set information and transmits the simultaneous transmission relay station set information to relay stations managed by the base station, and an relay station receives the simultaneous transmission relay station set information from the base station, determines, upon receipt of a data frame from the base station, a state of the relay station preset in relation to a receiving relay station for the data frame by comparing an ID of the receiving relay station included in the data frame with the simultaneous transmission relay station set information, and operates according to the preset state.

Abstract: An insert for a carrier board of a test handler is disclosed. In a first aspect, the latch block applying to the insert is detachably coupled to the insert body. The latch block can be reused, and thus this reduces wastage of resources and eliminates the insert replacement fee. In a second aspect, the insert pocket having hooks is detachably coupled to the insert body. The insert body can be reused. The latch unit is installed to the insert pocket, so that the damaged latch unit can be easily replaced. The insert forms a plurality of holes in the bottom of the loading part thereof, to expose the leads of the semiconductor devices through the holes downwardly. Thus, the insert can load semiconductor devices regardless of the dimensions of the semiconductor devices.

Abstract: The present disclosure relates to laser processing and a laser processing apparatus for processing materials using laser. Processing performed after loading a wafer on a work stage and a laser processing apparatus for implementing such processing, among others, are disclosed. The laser processing includes loading a wafer on a work stage; determining the number of chips formed on the wafer loaded on the work stage, performing chip defect inspection and aligning the wafer while moving the work stage; measuring a height of a surface of the wafer loaded on the work stage using a displacement sensor; monitoring output power of a processing laser using a power meter; and shifting the work stage while irradiating a laser beam on the wafer to process the wafer.

Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.

Abstract: A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.

Abstract: A word line driving circuit includes an address decoding signal generating unit and a word line voltage supply unit. The address decoding signal generating unit includes inverter chain receiving and delaying a first address decoding signal and outputting the delayed first address decoding signal. The word line voltage supply unit includes a pull-up driver that supplies the delayed first address signal to a selected word line in response to a second address decoding signal. The inverter chain includes an NMOS transistor outputting the delayed first address signal and a source terminal of the NMOS transistor receives a set voltage that is higher than a ground voltage and lower than a high voltage.

Abstract: The present disclosure relates to laser processing and a laser processing apparatus for processing materials using laser. Processing performed after loading a wafer on a work stage and a laser processing apparatus for implementing such processing, among others, are disclosed. The laser processing includes loading a wafer on a work stage; determining the number of chips formed on the wafer loaded on the work stage, performing chip defect inspection and aligning the wafer while moving the work stage; measuring a height of a surface of the wafer loaded on the work stage using a displacement sensor; monitoring output power of a processing laser using a power meter; and shifting the work stage while irradiating a laser beam on the wafer to process the wafer.

Abstract: A handover method according to one embodiment of the present invention comprises the steps of receiving the result of a cell measurement for a neighbor cell from a terminal, judging whether the neighbor cell is a near neighbor cell in accordance with the result of the cell measurement, calculating the ratio of the near neighbor cell to the total neighbor cells, and transmitting a command for a handover to a target cell to the terminal if the ratio exceeds the handover threshold value. The handover method of the present invention reduces interference between cells, and efficiently uses radio resources.