Abstract: The present invention provides a battery monitoring method, which is performed by a battery monitoring device, including: measuring a first voltage drop across both ends of a first shunt resistor of a bus bar electrically connected to a battery and a second voltage drop across both ends of a second shunt resistor, which is in parallel or serial connection with the first shunt resistor; calculating a first current and a second current flowing, respectively, through the first shunt resistor and the second shunt resistor using a first voltage drop value and a second voltage drop value; and determining a state of the battery using a difference between a first current value and a second current value. According to the present invention, it is possible to increase the reliability of monitoring information related to the battery's state by utilizing current values that have undergone linearity compensation and temperature compensation.

Abstract: A computing resource management system using software modularization in a cluster computing environment in which computing devices are connected, including an application process running on each computing device and an algorithm processing process configured to run independently of the application process and perform task processing on the application process, the computing resource management system including: a task managing system configured to receive a task request message from an application process requiring a task from each computing device; a process managing system configured to confirm an algorithm processing process of computing devices connected to the cluster computing environment, and determine whether there is an algorithm processing process in an idle state to which the application process requested for a task will be assigned; and a performed managing system configured to confirm a result of an application process whose task is performed by the algorithm processing process.

Abstract: The inventive concept provides a teaching method for teaching a transfer position of a transfer robot. The teaching method includes: searching for an object on which a target object to be transferred by the transfer robot is placed, based on a 3D position information acquired by a first sensor; and acquiring coordinates of a second direction and coordinates of a third direction of the object based on a data acquired from a second sensor which is a different type from the first sensor.

Abstract: In a driving system, first and second inverters are connected to a driving motor, one end of a stator winding through which 3-phase current flows is connected to an output line of the first inverter, and the other end of the stator winding is connected to an output line of the second inverter. A winding pattern of the driving motor includes: coils wound in slots defined in the stator and to which 3-phase current is applied; coils wound on innermost and outermost sides based on a direction toward a rotating shaft of the driving motor in the slots, and being energized by different AC phases; and coils disposed between a first coil located on the outermost side and a second coil located on the innermost side, and being energized by the same AC phases as those of the first and second coils.

Abstract: Disclosed herein are an apparatus and method for a multi-cloud service platform. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program may receive a service request from a user client device, generate a multi-cloud infrastructure service using multiple clouds in response to the service request, make the multiple clouds interoperate with mufti-cloud infrastructure in order to provide the multi-cloud infrastructure service, and generate a multi-cloud application runtime environment corresponding to the multi-cloud infrastructure service.

Abstract: Proposed are a home port and a substrate processing apparatus using the same. The home port is installed in the substrate processing apparatus to temporarily mount a nozzle for discharging a process liquid to a substrate, and includes a main body having a space therein, a nozzle holder provided at an upper portion of the main body and configured to mount the nozzle, an inclined surface formed below the nozzle holder in the space, a first supply pipe configured to discharge a rinse liquid to a tip of the nozzle, a second supply pipe configured to inject the rinse liquid into the main body, a conductive wire configured to electrically connect the inclined surface and the first supply pipe, and a first switch installed on the conductive wire.

Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.

Abstract: A hydrogen storage device includes a storage container having an accommodation space in an interior thereof, a first metal hydride material provided in the interior of the storage container and that stores hydrogen, and a second metal hydride material provided in the interior of the storage container and that stores the hydrogen at a pressure that is different from that of the first metal hydride material. An advantageous effect of restraining an excessive rise of a pressure of the storage container and enhancing safety and reliability may be obtained.

Abstract: A hydrogen storage system is disclosed and includes a storage unit including a plurality of unit storage containers, in which metal hydride materials are respectively provided in an interior thereof and which are connected to each other in parallel, and a thermal fluid line defining a thermal fluid passage, which passes via the plurality of unit storage containers continuously and through which a thermal fluid flows for heating or cooling the unit storage containers, thereby enhancing a storage performance and an efficiency of the hydrogen.

Abstract: A battery module includes a module housing including a first plate in which one side is open, a second plate coupled with the first plate to form an internal space, and a partition member disposed across the internal space to couple the first plate with the second plate; and a battery cell stack disposed in the internal space, in which a plurality of battery cells are stacked.

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.

Abstract: A non-volatile memory chip comprises a cell region that includes a first surface, a second surface opposite to the first surface, a first cell structure, and a second cell structure spaced apart from the first cell structure; a peripheral circuit region on the first surface of the cell region, and that includes a first peripheral circuit connected to the first cell structure, a second peripheral circuit connected to the second cell structure, and a connection circuit between the first and second peripheral circuits; a through via between the first and second cell structures and that extends from the second surface of the cell region to the connection circuit of the peripheral circuit region; a redistribution layer that covers the through via on the second surface of the cell region, is connected to the through via, and extends along the second surface; and a chip pad connected to the redistribution layer.

Abstract: A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.

Abstract: A semiconductor package includes a first layer including a first semiconductor chip and a first through via, a first redistribution layer disposed on a surface of the first layer, and including a first-first wiring and a second-first wiring, and a second layer including a second semiconductor chip, and stacked on the first layer. The first semiconductor chip includes a first-first buffer, and the first-first buffer is electrically connected between the first-first wiring and the second-first wiring.

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.