Abstract: The inventive concept relates to an apparatus for treating a substrate. In an embodiment, the apparatus includes a process chamber having a process space in which the substrate is treated with a fluid in a supercritical state, a support unit that supports the substrate in the process space, a fluid supply unit that supplies the fluid into the process space, a filler member disposed to face the substrate placed on the support unit in the process space, and a measurement unit that measures a state in the process space, the measurement unit being provided in the filler member.

Abstract: The food inputting apparatus according to the present invention comprises: a supply unit provided so as to supply food downwardly; a chute unit comprising a chute body through which food discharged from the supply unit falls and passes due to gravity; a shutter unit provided so as to be opened or closed in accordance with whether the food discharged from the chute unit is to be discharged into packaging material, and comprising a shutter body which, when closed, is positioned between the upper part of an upwardly opened opening of the packaging material and a chute outlet provided at the bottom end of the chute unit; and a suction unit for suctioning liquid that collects inside the shutter body when closed.

Abstract: A memory device is provided. The memory device comprises a memory cell array connected to a first bit line and a complementary bit line, a first bit line sense amplifier configured to sense, amplify and the first bit line signal output a first bit line signal and the complimentary bit signal output on a complementary bit line signal output on the first bit line and the complementary bit line, a charge transfer transistor connected to the first bit line sense amplifier and configured to be gated by a charge transfer signal of a first node, an offset transistor configured to connect the first node and a second node based on an offset removal signal and a pre-charging transistor connected between the second node and a pre-charging voltage line and the pre-charging transistor being configured to pre-charge the first bit line or the complementary bit line based on an equalizing signal.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.

Abstract: The present invention relates to a nanocomposite for detecting hydrogen sulfide; a method for preparing the same; a novel reactive fluorogenic compound to be used in the method; a kit for detecting hydrogen sulfide comprising the nanocomposite; and a method for providing information for the diagnosis of a disease, which causes abnormal secretion of hydrogen sulfide, by using the nanocomposite.

Abstract: There are provided a sense amplifier for sensing a multilevel cell and a memory device including the same. The sense amplifier is configured to sense the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data a cell voltage stored in a memory cell as the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data. The sense amplifier senses the MSB of the 2-bit data in a state in which a bit line is electrically disconnected from a holding bit line of the sense amplifier and senses the LSB of the 2-bit data in a state in which the cell bit line is electrically connected to the holding bit line. The sense amplifier is configured to equalize a pair of bit lines of the sense amplifier before sensing the MSB and the LSB of the 2-bit data. The sense amplifier is configured to restore to the memory cell the cell voltage corresponding to the sensed MSB and LSB of the 2-bit data.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A method for detecting biomaterial by means of a dye having a linear upconversion fluorescent property is provided. The method includes the steps of: i) preparing a fluorophore having a linear upconversion fluorescent property; ii) reacting the fluorophore and biomaterial to obtain a reaction complex thereof; iii) exciting the reaction complex by means of a light source having a longer wavelength than the maximum light-emitting wavelength of the fluorophore; and iv) detecting and measuring the light-emitting signal having a shorter wavelength than the wavelength of the excited light emitted from the excited reaction complex. A system and a kit for detecting biomaterial using a dye having a linear upconversion fluorescent property are also provided.

Abstract: A semiconductor memory device includes an error correction code (ECC) engine, a memory cell array, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes a normal cell region configured to store main data and a parity cell region configured to selectively store parity data which the ECC engine generates based on the main data, and sub data received from outside of the semiconductor memory device. The control logic circuit controls the ECC engine to selectively perform an ECC encoding and an ECC decoding on the main data and controls the I/O gating circuit to store the sub data in at least a portion of the parity cell region.

Abstract: A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.

Abstract: A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.

Abstract: A method for detecting biomaterial by means of a dye having a linear upconversion fluorescent property is provided. The method includes the steps of: i) preparing a fluorophore having a linear upconversion fluorescent property; ii) reacting the fluorophore and biomaterial to obtain a reaction complex thereof; iii) exciting the reaction complex by means of a light source having a longer wavelength than the maximum light-emitting wavelength of the fluorophore; and iv) detecting and measuring the light-emitting signal having a shorter wavelength than the wavelength of the excited light emitted from the excited reaction complex. A system and a kit for detecting biomaterial using a dye having a linear upconversion fluorescent property are also provided.

Abstract: Memory devices are provided. A memory device includes a voltage generation circuit that includes an offset compensator configured to receive a reference voltage and an offset code and to link the offset code to the reference voltage. The voltage generation circuit includes a comparator configured to compare the reference voltage linked to the offset code with a bit line pre-charge voltage and to output driving control signals. The voltage generation circuit includes a driver configured to output the bit line pre-charge voltage at a target level of the reference voltage in response to the driving control signals. The voltage generation circuit includes a background calibration circuit configured to generate the offset code for performing control so that a target short current flows through an output node of the driver from which the bit line pre-charge voltage is output. Related methods of generating a bit line pre-charge voltage are also provided.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.

Abstract: A sense amplifier includes a first sense amplification circuit electrically connected between a bit line, to which a multi-bit memory cell is also connected, and a complementary bit line. The first sense amplification circuit is configured to sense a least significant bit (LSB) of 2-bit data in the memory cell and latch the LSB in a first sensing bit line pair. A second sense amplification circuit is provided, which is configured to sense a most significant bit (MSB) of the 2-bit data and latch the MSB in a second sensing bit line pair. A switching circuit is provided, which is configured to selectively connect between bit lines of the first sensing bit line pair and bit lines of the second sensing bit line pair.

Abstract: There are provided a sense amplifier for sensing a multilevel cell and a memory device including the same. The sense amplifier is configured to sense the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data a cell voltage stored in a memory cell as the most significant bit (MSB) and the least significant bit (LSB) of 2-bit data. The sense amplifier senses the MSB of the 2-bit data in a state in which a bit line is electrically disconnected from a holding bit line of the sense amplifier and senses the LSB of the 2-bit data in a state in which the cell bit line is electrically connected to the holding bit line. The sense amplifier is configured to equalize a pair of bit lines of the sense amplifier before sensing the MSB and the LSB of the 2-bit data. The sense amplifier is configured to restore to the memory cell the cell voltage corresponding to the sensed MSB and LSB of the 2-bit data.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit, and a control logic circuit. The memory cell array includes a plurality of bank arrays, and each of the bank arrays includes dynamic memory cells. The control logic circuit generates a first control signal to control the I/O gating circuit and a second control signal to control the ECC engine, in response to an access address and a command. The control logic circuit controls the ECC engine to perform s-bit ECC encoding on a write data to be stored in a first page of at least one bank array, in response to a first command, and controls the ECC engine to perform t-bit ECC decoding on a first codeword read from the first page, in response to a second command.

Abstract: Memory devices are provided. A memory device includes a voltage generation circuit that includes an offset compensator configured to receive a reference voltage and an offset code and to link the offset code to the reference voltage. The voltage generation circuit includes a comparator configured to compare the reference voltage linked to the offset code with a bit line pre-charge voltage and to output driving control signals. The voltage generation circuit includes a driver configured to output the bit line pre-charge voltage at a target level of the reference voltage in response to the driving control signals. The voltage generation circuit includes a background calibration circuit configured to generate the offset code for performing control so that a target short current flows through an output node of the driver from which the bit line pre-charge voltage is output. Related methods of generating a bit line pre-charge voltage are also provided.

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.