Patents by Inventor Youseok Suh
Youseok Suh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190312025Abstract: An integrated circuit (IC) is fabricated with transistors and gated diodes having selected epitaxial growth. The transistors may be Field-Effect Transistors (FETs) for example, and more specifically, may be fin-based FETs (finFETs) where fins are fabricated, in part, using an epitaxial growth process. The IC is further fabricated with gated diodes. Selected gated diodes within the IC are fabricated using the epitaxial growth process on the fins of the gated diode to form an anode and a cathode. Other selected gated diodes are fabricated without using epitaxial growth processes to form the anode and the cathode. In still another aspect, selected gated diodes are fabricated with epitaxial growth processes on either the anode or the cathode, but not both. In an exemplary aspect, the other selected gated diodes are part of electrostatic discharge (ESD) protection circuits in an input/output (I/O) region of the IC.Type: ApplicationFiled: April 6, 2018Publication date: October 10, 2019Inventors: Youn Sung Choi, Youseok Suh, Kwanyong Lim
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Patent number: 10361215Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.Type: GrantFiled: July 6, 2018Date of Patent: July 23, 2019Assignee: Cypress Semiconductor CorporationInventors: Ming Sang Kwan, Shenqing Fang, Youseok Suh, Michael A. Van Buskirk
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Patent number: 10297606Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.Type: GrantFiled: January 11, 2017Date of Patent: May 21, 2019Assignee: Cypress Semiconductor CorporationInventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
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Publication number: 20180366473Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.Type: ApplicationFiled: July 6, 2018Publication date: December 20, 2018Applicant: Cypress Semiconductor CorporationInventors: Ming Sang Kwan, Shenqing Fang, Youseok Suh, Michael A. VAN BUSKIRK
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Patent number: 10038004Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.Type: GrantFiled: September 27, 2016Date of Patent: July 31, 2018Assignee: Cypress Semiconductor CorporationInventors: Ming Sang Kwan, Shenqing Fang, Youseok Suh, Michael A. Van Buskirk
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Publication number: 20180076139Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.Type: ApplicationFiled: November 15, 2016Publication date: March 15, 2018Inventors: Yanxiang LIU, Haining YANG, Youseok SUH, Jihong CHOI, Junjing BAO
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Publication number: 20170170187Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.Type: ApplicationFiled: January 11, 2017Publication date: June 15, 2017Applicant: Cypress Semiconductor CorporationInventors: Youseok Suh, Sung-Yong Chung, Ya-Fen LIN, Yi-Ching Jean Wu
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Patent number: 9570458Abstract: Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.Type: GrantFiled: February 12, 2014Date of Patent: February 14, 2017Assignee: Cypress Semiconductor CorporationInventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
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Publication number: 20170018555Abstract: A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.Type: ApplicationFiled: September 27, 2016Publication date: January 19, 2017Inventors: Ming Sang Kwan, Shenqing Fang, Youseok Suh, Michael A. Van Buskirk
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Patent number: 9514824Abstract: A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.Type: GrantFiled: December 18, 2013Date of Patent: December 6, 2016Assignee: Cypress Semiconductor CorporationInventors: Ya-Fen Lin, Colin S. Bill, Takao Akaogi, Youseok Suh
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Patent number: 9449690Abstract: A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias voltage is applied to a fourth wordline adjacent to the source side of the first wordline. A pass voltage is also applied to the remaining wordlines that do not have one of a bias voltage and a program voltage applied, the pass voltage a selected voltage level.Type: GrantFiled: April 3, 2013Date of Patent: September 20, 2016Assignee: Cypress Semiconductor CorporationInventors: Swaroop Kaza, Youseok Suh, Di Li, Sameer S. Haddad
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Patent number: 9276007Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: January 29, 2014Date of Patent: March 1, 2016Assignee: Cypress Semiconductor CorporationInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Patent number: 9190531Abstract: An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.Type: GrantFiled: December 21, 2012Date of Patent: November 17, 2015Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Meng Ding, YouSeok Suh, Shenqing Fang, Kuo-Tung Chang
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Publication number: 20140312409Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: ApplicationFiled: January 29, 2014Publication date: October 23, 2014Applicant: SPANSION LLCInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Hapreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
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Publication number: 20140301146Abstract: A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias voltage is applied to a fourth wordline adjacent to the source side of the first wordline. A pass voltage is also applied to the remaining wordlines that do not have one of a bias voltage and a program voltage applied, the pass voltage a selected voltage level.Type: ApplicationFiled: April 3, 2013Publication date: October 9, 2014Applicant: Spansion LLCInventors: Swaroop KAZA, Youseok SUH, Di LI, Sameer HADDAD
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Patent number: 8809936Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.Type: GrantFiled: July 31, 2006Date of Patent: August 19, 2014Assignees: Globalfoundries Inc., Spansion LLCInventors: Lei Xue, Rinji Sugino, YouSeok Suh, Hidehiko Shiraiwa, Meng Ding, Shenqing Fang, Joong Jeon
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Publication number: 20140159138Abstract: Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.Type: ApplicationFiled: February 12, 2014Publication date: June 12, 2014Applicant: SPANSION LLCInventors: YouSeok SUH, Sung-Yong CHUNG, Ya-Fen LIN, Yi-Ching WU
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Publication number: 20140104957Abstract: A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Applicant: SPANSION LLCInventors: Ya-Fen LIN, Colin BILL, Takao AKAOGI, Youseok SUH
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Patent number: 8692310Abstract: Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.Type: GrantFiled: February 9, 2009Date of Patent: April 8, 2014Assignee: Spansion LLCInventors: YouSeok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Wu
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Patent number: 8642441Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.Type: GrantFiled: December 15, 2006Date of Patent: February 4, 2014Assignee: Spansion LLCInventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Harpreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang