Abstract: A NAND flash memory cell string having scaled down select gates. The NAND flash memory cell string includes a first select gate that has a width of 140 nm or less and a plurality of wordlines that are coupled to the first select gate. Gates associated with the plurality of wordlines are formed of p+ polysilicon. A second select gate that has a width of 140 nm or less is coupled to the plurality of wordlines.

Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Abstract: A flash memory cell includes a charge storage element that includes at least a first layer and a second layer. One of the layers includes silicon-rich silicon nitride and the other layer includes silicon nitride. More specifically, the ratio of silicon-to-nitrogen in the first layer is greater than the ratio of silicon-to-nitrogen in the second layer.

Abstract: An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.

Abstract: Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Adjacent gate stacks are a second distance apart. A cell spacer material layer is deposited and is etched to form a spacer about sidewalls of each gate stack. A source/drain impurity doped region is formed adjacent a first gate stack and a last gate stack. The first distance and the second distance are such that, when a voltage is applied to a gate stack during a READ operation, a fringing field is created between the control gate of the gate stack and the substrate and is sufficient to invert a portion of the substrate between the gate stack and an adjacent gate stack.

Abstract: A memory device (100) may include a substrate (110), a dielectric layer (210) formed on the substrate (110) and a charge storage element (220) formed on the dielectric layer (210). The memory device (100) may also include an inter-gate dielectric (230) formed on the charge storage element (220), a barrier layer (240) formed on the inter-gate dielectric (230) and a control gate (250) formed on the barrier layer (240). The barrier layer (240) prevents reaction between the control gate (250) and the inter-gate dielectric (230).

Abstract: A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

Abstract: A memory system includes a substrate, forming a first insulator layer over the substrate, forming a charge-storage layer over the first insulator layer, forming a second insulator layer over the charge-storage layer, and forming a depletion gate having a depletion phenomenon over the second insulator layer.

Abstract: A memory system includes a substrate, forming a first insulator over the substrate, forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator, and forming a second insulator over the charge trap layer.

Abstract: A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.

Abstract: A memory system includes a substrate, forming an insulator over the substrate, forming a gate layer over the insulator, forming a stability layer over the gate layer, and forming a conductive layer over the stability layer.

Abstract: A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.

Abstract: A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.

Abstract: A method for manufacturing a memory device that includes using a gap-filling material that inhibits charge coupling between memory devices. A semiconductor material is provided that has an active region and an isolation region. A charge trapping structure is formed over the active region and a layer of semiconductor material is formed over the charge trapping structure and the isolation region. A masking structure having sidewalls is formed on the layer of semiconductor material. Spacers are formed adjacent the sidewalls and the layer of semiconductor material is etched to form one or more conductive strips having opposing sides. The one or more conductive strips are formed over the active region. A dielectric material is formed adjacent to the opposing sides of each conductive strip. The dielectric material serves as a gap-filling material. A layer of semiconductor material is formed over the one or more conductive strips.

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.

Abstract: An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Abstract: A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.

Abstract: A memory device may include a substrate, a dielectric layer formed on the substrate and a charge storage element formed on the dielectric layer. The memory device may also include an inter-gate dielectric formed on the charge storage element, a barrier layer formed on the inter-gate dielectric and a control gate formed on the barrier layer. The barrier layer prevents reaction between the control gate and the inter-gate dielectric.