Abstract: An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contact region couples electrically to a body of the SOI transistor. The gate controls current flow between the first and second source regions and a drain region of the transistor. The first isolation region is disposed between the first source region and the body contact region. The second isolation region is disposed between the second source region and the body contact region.

Abstract: An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contact region couples electrically to a body of the SOI transistor. The gate controls current flow between the first and second source regions and a drain region of the transistor. The first isolation region is disposed between the first source region and the body contact region. The second isolation region is disposed between the second source region and the body contact region.

Abstract: An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contact region couples electrically to a body of the SOI transistor. The gate controls current flow between the first and second source regions and a drain region of the transistor. The first isolation region is disposed between the first source region and the body contact region. The second isolation region is disposed between the second source region and the body contact region.

Abstract: An integrated circuit (IC) includes one or more silicon-on-insulator (SOI) transistors. Each SOI transistor includes a first source region, a second source region, a drain region, a body contact region, a gate, and first and second isolation regions. The body contact region couples electrically to a body of the SOI transistor. The gate controls current flow between the first and second source regions and a drain region of the transistor. The first isolation region is disposed between the first source region and the body contact region. The second isolation region is disposed between the second source region and the body contact region.

Abstract: A method for making a self-aligned isolated memory core for a flash memory wafer includes the steps of establishing control gates for memory cells in the core by depositing a first polysilicon layer on a silicon substrate, etching the first layer, and depositing a second polysilicon layer on the substrate, with the polysilicon layers being separated by an interpoly dielectric layer. Then, after the control gates have been established, isolation trenches are formed in the silicon substrate between regions by self-aligned etching processes.

Abstract: A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

Abstract: A device structure and method for a non-volatile semiconductor device comprises a trenched floating gate and a control gate and further includes a source region, a drain region, a channel region, and an inter-gate dielectric layer. The trenched floating gate is formed in a trench etched into the semiconductor substrate. The trenched floating gate has a top surface which is substantially planar with a top surface of the substrate. The source and drain region have a depth approximately equal to or greater than the depth of the trench and partially extend laterally underneath the bottom of the trench. The inter-gate dielectric layer is formed on the top surface of the trenched floating gate, and the control gate is formed on the inter-gate dielectric layer. In one embodiment, the device structure also includes sidewall dopings that are implanted regions formed in the semiconductor substrate which extend substantially vertically along the length of the trench.

Abstract: A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region a drain region and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.

Abstract: A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

Abstract: A method and arrangement for forming a recessed spacer to prevent the gouging of device junctions during a contact etch or local interconnect etch process deliberately overetches the spacer material layer during the formation of sidewall spacers on the sidewalls of a gate. The exposed portions of the gate sidewalls are then covered by silicide formed during a silicidation process. The formation of the suicide on the gate sidewalls prevents the sidewall spacers from being preferentially attacked during a local interconnect etch or contact etch.

Abstract: A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

Abstract: A semiconductor device includes a wafer having a semiconductor layer with source, body and drain regions. A electrically-conducting region of the semiconductor region overlaps and electrically couples the source region and the body region. The electrical coupling of the source and body regions reduces floating body effects in the semiconductor device. A method of constructing the semiconductor device utilizes spacers, masking, and/or tilted implantation to form an source-body electrically-conducting region that overlaps the source and body regions of the semiconductor layer, and a drain electrically-conducting region that is within the drain region of the semiconductor layer.

Abstract: A fully recessed device structure and method for low power applications comprises a trenched floating gate and a trenched control gate formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography for low power applications. The trenched floating gate is electrically isolated from the trenched control gate by an inter-gate dielectric layer formed inside the trench and on a top surface of the trenched floating gate. The trenched control gate is formed on a top surface of the inter-gate dielectric layer and preferably, has a top surface which is substantially planar with a top surface of the semiconductor substrate. The fully recessed structure further comprises a buried source region, a buried drain region and a channel region. The buried source region and the buried drain region are formed in the well junction region and are laterally separated by the trench.

Abstract: A system and method for providing a trench in a material using semiconductor processing is disclosed. In one aspect, the method and system include (a) providing a spacer, (b) etching the material, and (c) repeating steps (a) and (b) a sufficient number of times to achieve a desired profile for the trench. The spacer is insensitive to an etch of the material. The material is exposed adjacent to the spacer. In another aspect, the method and system include (a) providing a spacer, (b) etching the material, (c) stripping the spacer, and (d) repeating steps (a) through (c) until a desired profile for the trench is achieved. Each time steps (a) through (c) are repeated via step (d), a thinner spacer is provided. In addition, the spacer is insensitive to an etch of the material. The material is exposed adjacent to the spacer.

Abstract: Complementary metal-oxide-semiconductor (CMOS) transistors (18,22) are formed with vertical channel regions (30,52) on an insulator substrate (14). Highly doped polysilicon gates (44,68) are formed in trenches (36,58) to extend laterally around the channel regions (30,52) as insulatively displaced therefrom by gate insulators (41,62) that are grown on the sidewalls of the trenches (36,58). The transistors (18,22), which are formed in respective mesas (20,24) have deeply implanted source regions (28,50) that are ohmically connected to the semiconductor surface via respective source connector regions (34,70).

Abstract: A non-volatile semiconductor device structure and method for low power applications comprises a trenched floating gate and corner dopings and further includes a well junction region with a source region and a drain region therein, and includes a channel region, an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate and has a top surface which is substantially planar with a top surface of the semiconductor substrate. The source and drain regions are laterally separated by the trench in which the trenched floating gate is formed and have a depth which is approximately less than the depth of the trench. The channel region is formed beneath a bottom surface of the trench and is doped to form a depletion type channel region.

Abstract: A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors having transistor gates formed of a polysilicon layer and resistors formed of the same polysilicon layer. In accordance with a second embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors, a dielectric layer overlying the NMOS transistors, and polysilicon resistors passing through the dielectric layer to connect the NMOS transistors to a first metal layer. The dielectric layer, deposited on the NMOS transistors, defines holes exposing drain regions in the NMOS transistors. A polysilicon layer is deposited on the dielectric layer to fill the holes, and the excess polysilicon is removed.

Abstract: A device structure and method for a non-volatile semiconductor device comprises a trenched floating gate and a control gate and further includes a source region, a drain region, a channel region, and an inter-gate dielectric layer. The trenched floating gate is formed in a trench etched into the semiconductor substrate. The trenched floating gate has a top surface which is substantially planar with a top surface of the substrate. The source and drain have a depth approximately equal to or greater than the depth of the trench and partially extend laterally underneath the bottom of the trench. The inter-gate dielectric layer is formed on the top surface of the trenched floating gate, and the control gate is formed on the inter-gate dielectric layer. In one embodiment, the device structure also includes sidewall dopings that are implanted regions formed in the semiconductor substrate which extend substantially vertically along the length of the trench.

Abstract: A method for extracting a channel length between a source and a drain in a substrate of a transistor is disclosed herein. The method includes forward biasing the source with respect to the substrate to inject a charge into the substrate, collecting the charge at the drain, and calculating the channel length from the charge collected at the drain.

Abstract: A method of fabricating an integrated circuit with trenches, without parasitic edge transistors, for isolating FET transistors from each other without degrading the FETs operating characteristics by junction leakage, breakdown or shorting when a metal silicide is used in the source/drain regions. A silicon wafer, is formed with a gate electrode material on a gate insulating layer before forming the trenches for isolation. Now, with an etch protective layer on the gate electrode, trenches are etched and filled with an insulating material in the gate electrode material, the gate insulating layer and the silicon wafer to isolate the active regions. After the gate electrode material is etched to define the gate electrodes, the tops of gate electrodes are in essentially the same plane as the tops of the trenches. Preferably in the fabrication process, sidewalls are formed on the walls of the trenches and the gate electrodes.