Abstract: A method for making a ULSI MOSFET includes establishing a gate void in a field oxide layer above a silicon substrate, after source and drain regions with associated source and drain extensions have been established in the substrate. A gate electrode is deposited in the void and gate spacers are likewise deposited in the void on the sides of the gate electrode, such that the gate electrode is spaced from the walls of the void. The spacers, not the gate electrode, are located above the source/drain extensions, such that fringe coupling between the gate electrode and the source and drain extensions is suppressed.

Abstract: Double density non-volatile memory cells having a trench structure are formed in a substrate, thereby facilitating miniaturization, improved planarization and low power programming and erasing. Each double density cell comprises two floating gates and a common control gate. Each pair of double density cells shares a common source region. Embodiments include forming first and second trenches in a substrate and depositing a tunnel dielectric layer in each trench. Polycrystalline silicon is then deposited filling each trench and a hole is etched forming two floating gate electrodes in each trench. An interpoly dielectric layer is then formed and a substantially T-shaped control gate electrode is deposited filling the hole between the floating gates and extending on the substrate.

Abstract: A non-volatile semiconductor device structure and method for low power applications comprises a trenched floating gate and corner dopings and further includes a well junction region with a source region and a drain region therein, and includes a channel region, an inter-gate dielectric layer, and a control gate. The trenched floating gate is formed in a trench etched into the semiconductor substrate and has a top surface which is substantially planar with a top surface of the semiconductor substrate. The source and drain regions are laterally separated by the trench in which the trenched floating gate is formed and have a depth which is approximately less than the depth of the trench. The channel region is formed beneath a bottom surface of the trench and is doped to form a depletion type channel region.

Abstract: A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate.

Abstract: Apparatus and methods for determining the robustness and angle sensitivity of a device to soft errors generated by alpha-particle and/or cosmic ray strikes. In one embodiment, the method includes the steps of producing a light pulse with a given light pulse energy; applying the light pulse to the device at a predetermined location and a predetermined angle; varying the light pulse energy; and detecting soft errors in the device.

Abstract: A method of fabricating integrated circuit including field effect transistors (FET) having source and drain regions and a gate and with LOCOS isolation by selectively forming, after the FETs are fabricated, trench openings in the source or drain regions or in the LOCOS isolation to maximize the isolation in selected areas while reducing the amount of silicon used by the isolation.

Abstract: A trench isolation structure in a semiconductor substrate includes a trench opening in the surface of the substrate and a seamless oxide layer filling the trench. The seamless oxide layer is formed by forming a first oxide layer in the trench, adding a silicon material overlying the first oxide layer and within a gap on the first oxide layer between the trench sidewalls that tend to be produced in the preceding step, and oxidizing the silicon material to form a second oxide layer. The deposited silicon material expands during oxidation, filling the trench opening to produce a seamless oxide fill of the trench. This seamless trench isolation structure prevents accumulation of materials that reduce the yield of the finished semiconductor product.

Abstract: A field effect transistor is formed across a one or more trenches (26) or bars (120), thereby increasing the effective width of the channel region and the current-carrying capacity of the device.

Abstract: The present invention accurately determines a first parasitic capacitance component between a conductive gate region to a drain local interconnect of a real field effect transistor, and determines a second parasitic capacitance component between the conductive gate region to a source local interconnect of the real field effect transistor. A virtual field effect transistor is fabricated on a dielectric in order to determine the parasitic capacitance component between just the gate and the drain or source local interconnect of the real field effect transistor. The virtual field effect transistor includes a virtual drain local interconnect, a virtual source local interconnect, and a virtual conductive gate region fabricated on the dielectric with a respective size and positions relative to each other that are substantially the same as that of the drain and source local interconnects and the gate, respectively, of the real field effect transistor.

Abstract: The invention provides a method and apparatus for calculating gate length and source/drain gate overlap, by measuring gate capacitance. The invention uses previously known fringe capacitance C.sub.fr and unit capacitance C.sub.OX. The invention measures gate capacitance C.sub.g, when the gate is accumulatively biased, and solves for overlap capacitance C.sub.OV using the equation C.sub.OV =(C.sub.g -2C.sub.fr)/2 or C.sub.OV =(C.sub.gg -C.sub.gb -2C.sub.fr)/2. The invention then measures the gate capacitance C.sub.g when the gate to source/drain voltage is set to inversion bias and a zero voltage is applied between the source/drain and the substrate, and solves for the channel capacitance C.sub.ch using the equation C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV. The invention calculates the channel capacitance C.sub.ch where C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV and then calculates gate length where gate length L.sub.g =(2C.sub.OV +C.sub.ch)/C.sub.OX and the effective gate length L.sub.eff =C.sub.ch /C.sub.OX.

Abstract: A combination vertical MOSFET and JFET device (18,22) is formed in a mesa (20,24) of semiconductor material. A top gate (44,68) of the device is formed by creating a preferably annular trench (36,58) that extends downwardly from the surface of the semiconductor layer, creating a thin gate insulator (41,62) on the bottom and sidewalls of this trench, and filling the trench with highly doped polysilicon. A buried gate region (28,50) is formed by implanting the semiconductor layer, prior to top gate formation, such that the buried gate region is laterally coextensive with the mesa. An upper boundary (29,54) of the buried gate region is spaced below the bottom of the trench and spaced from the semiconductor surface. Upon application of a suitable voltage, the buried gate region and the top gate region coact to invert the conductivity type of the channel region, permitting transistor operation between the source region and the drain region.

Abstract: A dual material gate is effectively fabricated for a field effect transistor having a short channel length of submicron and nanometer dimensions such that disadvantageous short channel effects are minimized. Generally, the method of the present invention includes a step of forming a first material gate portion on a gate dielectric. The first material gate portion has a source side and a drain side, and an aspect of the present invention further includes the step of depositing a spacer dielectric layer on the source side and the drain side of the first material gate portion. An aspect of the present invention also includes the step of implanting heavy ions into the spacer dielectric layer at an angle such that the spacer dielectric layer at the drain side of the first material gate portion is substantially not implanted with the heavy ions. The spacer dielectric layer is then selectively etched such that any portion of the spacer dielectric layer that is implanted with the heavy ions is etched.

Abstract: A fully recessed device structure and method for low power applications comprises a trenched floating gate and a trenched control gate formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography for low power applications. The trenched floating gate is electrically isolated from the trenched control gate by an inter-gate dielectric layer formed inside the trench and on a top surface of the trenched floating gate. The trenched control gate is formed on a top surface of the inter-gate dielectric layer and preferably, has a top surface which is substantially planar with a top surface of the semiconductor substrate. The fully recessed structure further comprises a buried source region, a buried drain region and a channel region. The buried source region and the buried drain region are formed in the well junction region and are laterally separated by the trench.

Abstract: A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate.

Abstract: Double density non-volatile memory cells having a trench structure are formed in a substrate, thereby facilitating miniaturization, improved planarization and low power programming and erasing. Each double density cell comprises two floating gates and a common control gate. Each pair of double density cells shares a common source region. Embodiments include forming first and second trenches in a substrate and depositing a tunnel dielectric layer in each trench. Polycrystalline silicon is then deposited filling each trench and a hole is etched forming two floating gate electrodes in each trench. An interpoly dielectric layer is then formed and a substantially T-shaped control gate electrode is deposited filling the hole between the floating gates and extending on the substrate.

Abstract: A method for making a ULSI MOSFET includes establishing a void in a field oxide layer on a silicon substrate and filling the center of the void with a gate electrode. A high-k gate insulator is sandwiched between the gate electrode and the substrate. Around the void, a low-k gate spacer is formed, with the gate spacer being disposed directly above the source and drain extensions of the MOSFET.

Abstract: A Metal Oxide Semiconductor (MOS) transistor and method for improving device scaling comprises a trenched polysilicon gate formed within a trench etched in a semiconductor substrate and further includes a source region, a drain region, and a channel region. The source and drain region are laterally separated by the trench in which the trenched polysilicon gate is formed and partially extend laterally beneath the bottom surface of the trench. The channel region is formed in the silicon substrate beneath the bottom surface of the trench. In one embodiment, the top surface of the trenched polysilicon gate is substantially planar to the substrate surface. In another embodiment, the top surface and a portion of the trenched polysilicon gate are disposed above the substrate surface.

Abstract: Self-aligned silicide contacts having a height that is at least about equal to the gate height are formed by depositing silicon over active regions of the substrate, depositing a refractory metal over the silicon, and heating the silicon and the refractory metal. The deposited silicon may be amorphous silicon in which case the deposition temperature can be as low as 580.degree. C. If polysilicon is deposited, the deposition temperature has to be at least 620.degree. C.

Abstract: A method and apparatus that uses gate-to-substrate capacitance with varying amounts of source/drain junction bias to measure channel lateral doping profile by applying a series of different voltages between the source/drain and the substrate. The gate capacitance is measured for the different voltages. The capacitance is used to calculate the depletion width. From the depletion width, channel doping is calculated. Using this method direct evidence of a localized Boron pile up at source/drain edge is shown.

Abstract: A trench isolation structure in a semiconductor substrate includes a trench opening in the surface of the substrate and a seamless oxide layer filling the trench. The seamless oxide layer is formed by forming a first oxide layer in the trench, adding a silicon material overlying the first oxide layer and within a gap on the first oxide layer between the trench sidewalls that tend to be produced in the preceding step, and oxidizing the silicon material to form a second oxide layer. The deposited silicon material expands during oxidation, filling the trench opening to produce a seamless oxide fill of the trench. This seamless trench isolation structure prevents accumulation of materials that reduce the yield of the finished semiconductor product.