Abstract: An electronic device is provided with a display such as a liquid crystal display. The display has a layer of liquid crystal material sandwiched between an upper display layer such as a color filter layer and a lower display layer such as a thin-film-transistor layer. An upper polarizer is formed on the upper surface of the color filter layer. A lower polarizer is formed on the lower surface of the thin-film-transistor layer. To protect display layers such as the color filter layer and the thin-film-transistor layer, a coating is deposited on a peripheral edge of the display layer. A laser is used to cut through portions of the polarizer that overhang the display layer while also cutting through the coating on the peripheral edge of the display layer. Following laser trimming operations, the coating is flush with an edge surface of the polarizer.

Abstract: Devices and methods for increasing the aperture ratio and providing more precise gray level control to pixels in an active matrix organic light emitting diode (AMOLED) display are provided. By way of example, one embodiment includes disposing a gate insulator and an interlayer dielectric material between a gate electrode of a thin-film transistor of a driving circuit and a channel of the thin-film transistor. The improved structure of the driving circuit facilitates a higher voltage range for controlling the gray level of the pixels, and may increase the aperture ratio of the pixels.

Abstract: Devices and methods for increasing the aperture ratio and providing more precise gray level control to pixels in an active matrix organic light emitting diode (AMOLED) display are provided. By way of example, one embodiment includes disposing a gate insulator between a gate of a driving thin-film transistor and a gate of a circuit thin-film transistor. The improved structure of the display facilitates a higher voltage range for controlling the gray level of the pixels, and may increase the aperture ratio of the pixels.

Abstract: An electronic device is provided with a display such as a liquid crystal display mounted in an electronic device housing. The display has a layer of liquid crystal material sandwiched between an upper display layer such as a color filter layer and a lower display layer such as a thin-film-transistor layer. An upper polarizer is formed on the upper surface of the color filter layer. A lower polarizer is formed on the lower surface of the thin-film-transistor layer. To protect display layers such as a glass color filter layer substrate for the color filter layer from damage during polarizer trimming operations, a coating is deposited on a peripheral edge of the glass color filter layer substrate. The coating may be formed from an elastomeric polymer such as silicone and may remain in place or may be removed following trimming operations.

Abstract: Embodiments of the present disclosure relate to devices and methods for reducing the resistance level of top electrodes in top emission AMOLED displays. By way of example, one embodiment includes disposing a metal frame between the top electrode and an insulating layer. The present disclosure also relates to methods for making such a display in reduced number of process steps, including certain techniques for combining certain steps into one process step.

Abstract: A TFT stack for a liquid crystal display is provided. The TFT stack includes a silicon layer that includes a heavily doped region, a non-doped region, and a lightly doped region between the heavily doped region and the non-doped region. The heavily doped region is hydrogenated. The TFT stack also includes an insulation layer that includes a first portion formed over the lightly doped region and a second portion disposed over the non-doped region and a gate metal electrode layer formed over the second portion of the non-doped region. The TFT stack also includes a first dielectric layer disposed over the gate metal electrode and over the first portion of the insulation layer. The heavily doped region is hydrogenated to reduce the dependence of the capacitance between the gate metal electrode and the conductive layer Cgd upon a bias voltage being applied between the gate metal electrode and the conductive layer.

Abstract: An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer.

Abstract: An LCD panel transmits the display data to sub-pixels in a zigzag pattern through a data line. The variation of the feed-through voltages of the sub-pixels may be modified by adjusting the ratios of the channel widths and the channel lengths of the TFTs in the sub-pixels to some predetermined ratios, or by adjusting the compensation capacitance to the coupling capacitance of the TFTs of the sub-pixels.

Abstract: A display device having slim border-area architecture is disclosed. The display device includes a substrate, a plurality of data lines, a plurality of gate lines, a plurality of auxiliary gate lines and a driving module. The substrate includes a display area and a border area. The data lines, the gate lines and the auxiliary gate lines are disposed in the display area. The driving module is disposed in the border area. The gate lines are crossed with the data lines perpendicularly. The auxiliary gate lines are parallel with the data lines. Each auxiliary gate line is electrically connected to one corresponding gate line. The data and auxiliary gate lines are electrically connected to the driving module based on an interlace arrangement. Further disclosed is a driving method for delivering gate signals provided by the driving module to the gate lines via the auxiliary gate lines.

Abstract: A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line.

Abstract: A structure of X-ray detector includes a Si-rich dielectric material for serving as a photo-sensing layer to increase light sensitivity. The fabrication method of the X-ray detector including the Si-rich dielectric material needs less photolithography-etching processes, so as to reduce the total thickness of thin film layers and decrease process steps and cost.

Abstract: A display device includes a substrate, gate lines, data lines, gate tracking lines, and dummy gate tracking lines. The gate lines and the data lines are arranged perpendicularly. Each gate tracking line is disposed between one parts of two adjacent data lines, and substantially parallel to the data lines. Each dummy gate tracking line is electrically disconnected to the gate lines, disposed between other parts of two adjacent data lines, and substantially parallel to the data lines.

Abstract: A computer managing method includes the following steps. Firstly, a blade server system with M blade server units, which includes a number of server blades and a modular management blade (MMB), is provided, wherein the M MMBs are connected with each other via network paths and M is a natural number greater than 1. Then a master MMB among the M MMBs are selected in response to first user operation event. Next, the network parameter data of the master MMB are set in response to second user operation event. Then network topology of the master MMB and the rest of M?1 MMBs are obtained via the master MMB. After that, the rest of M?1 MMBs are driven for utilizing a network protocol service so that the M?1 MMBs are able to receive network parameter data from the master MMB and carry out parameter setting accordingly.

Abstract: An LCD panel transmits the display data to sub-pixels in a zigzag pattern through a data line. The variation of the feed-through voltages of the sub-pixels may be modified by adjusting the ratios of the channel widths and the channel lengths of the TFTs in the sub-pixels to some predetermined ratios, or by adjusting the compensation capacitance to the coupling capacitance of the TFTs of the sub-pixels.

Abstract: This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.

Abstract: An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain.

Abstract: An operation method for a server system includes: (A) under control of a hardware abstraction layer (HAL), a plurality of node management units sharing a hardware resource; (B) if one of the node management units needs to use the hardware resource, the node management unit sending an instruction or a data to the HAL and accordingly the HAL using the hardware resource in represent of the node management unit; and (C) if an external instruction is received, the HAL identifying which transmission port of the hardware resource receives the external instruction, so to send the external instruction to a corresponding node management unit, and after the external instruction is executed, the corresponding node management unit sending back an information to the HAL so that the HAL sends back the information to an external system administrator.

Abstract: An active device array substrate including a substrate, scan lines, data lines, active devices, a first dielectric layer, a common line, a second dielectric layer, a patterned conductive layer, a third dielectric layer, and pixel electrodes is provided. At least a part of the active devices are electrically connected to the scan lines and the data lines. The first dielectric layer covers the scan lines, the data lines and the active devices. The common line is disposed on the first dielectric layer. The second dielectric layer covers the common line and the first dielectric layer. The patterned conductive layer is disposed on the second dielectric layer. The third dielectric layer covers the patterned conductive layer and the second dielectric layer. The pixel electrodes are disposed on the third dielectric layer and electrically connected to the patterned conductive layer and the active devices.

Abstract: A pixel array is located on a substrate and includes a plurality of pixel sets. Each of the pixel sets includes a first scan line, a second scan line, a data line, a data signal transmission line, a first pixel unit, and a second pixel unit. The data line is not parallel to the first and the second scan lines. The data signal transmission line is disposed parallel to the first and the second scan lines and electrically connected to the data line. Distance between the first and the second scan lines is smaller than distance between the data signal transmission line and one of the first and the second scan lines. The first pixel unit is electrically connected to the first scan line and the data line. The second pixel unit is electrically connected to the second scan line and the data line.

Abstract: A display panel including an active device array substrate, an opposite substrate and a display medium is provided. The active device array substrate includes a substrate, scan lines, data lines, pixel units, and data signal transmission lines. The scan lines and data lines define a plurality of pixel regions on the substrate. Each pixel unit is disposed within one of the pixel regions respectively, and each pixel unit includes a plurality of sub-pixel units. The sub-pixel units within the same pixel unit are electrically connected with the same data line, and each sub-pixel unit within the same pixel unit is electrically connected with one of the scan lines respectively. Each data signal transmission line is electrically connected with one of the data lines, and an extending direction of the data signal transmission line is substantially parallel with an extending direction of the scan lines.