Abstract: A switched beam smart antenna apparatus is disclosed including: a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth beam adjusting elements; a first, a second, a third, and a fourth beam control modules; a first, a second, a third, and a fourth radiation strips positioned within an area surrounded by the first to eighth beam adjusting elements; and a radiation strip control module for selecting either the first and second radiation strips or the third and fourth radiation strips to transmit signals. When the first beam control module conducts the first and second beam adjusting elements, the third beam control module does not conduct the fifth and sixth beam adjusting elements. When the second beam control module conducts the third and fourth beam adjusting elements, the fourth beam control module does not conduct the seventh and eighth beam adjusting elements.

Abstract: A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.

Abstract: A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode.

Abstract: An exemplary display device includes multiple pixels, first through third gate lines and a data line. The pixels include first through third pixels. The first through third gate lines respectively are electrically coupled with the first through third pixels and for deciding whether to enable the first through third pixels. The first pixel is electrically coupled to the data line to receive a display data provided by the data line. The second pixel is electrically coupled to the first pixel to receive a display data provided by the data line through the first pixel. The third pixel is electrically coupled to the second pixel to receive a display data provided by the data line through both the first pixel and the second pixel. A display driving method adapted to be implemented in the display device also is provided.

Abstract: A heat-dissipation fan includes a first plate, a second plate, a ring wall, a spacing rib, a stator and a fan wheel. The first plate comprises a vent, and an accommodating space can be defined by the first plate, the second plate and the ring wall. The spacing rib is disposed at the accommodating space. A passage is formed between the spacing rib and the ring wall, and an end portion of the spacing rib and the ring wall are spaced apart to form an opening. The passage is in communication with the vent, and the opening is in communication with the passage and the accommodating space. The fan wheel can be driven by the stator, and the dust adhered to the accommodating space may be discharged through the opening, the passage and the vent via airflow generated by rotating fan wheel.

Abstract: An active device array substrate includes a substrate, scan lines disposed on the substrate, data lines intersected with the scan lines, scan signal transmission lines, and pixel units. The scan signal transmission lines are intersected with the scan lines. Each scan signal transmission line connects one scan line through a node. The pixel unit electrically connects the corresponding data line and the corresponding scan line and includes an active device and a pixel electrode. The active device has a gate, a source, and a drain. The pixel electrode electrically connects the drain. In the pixel units not adjacent to the nodes, a gate-to-drain capacitance of each active device is Cgd1. In the pixel units adjacent to the nodes, the gate-to-drain capacitances of some active devices are Cgd2, the gate-to-drain capacitances of the other active devices are Cgd1, and Cgd1?Cgd2.

Abstract: A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.

Abstract: A method for driving a pixel of a panel includes: during a first frame period: generating N different first pixel driving signals according to a first grayscale level; and during N driving time periods included in the first frame period, utilizing different first pixel driving signals in the N first pixel driving signals to orderly drive the pixel, respectively; and during a second frame period: generating N different second pixel driving signals according to a second grayscale level; and during N driving time periods included in the second frame period, utilizing different second pixel driving signals in the N second pixel driving signals to orderly drive the pixel, respectively. A first pixel driving signal of the N first pixel driving signals and a second pixel driving signal of the N second pixel driving signals that correspond to a same driving order have different signal polarities.

Abstract: An LCD panel transmits the display data to sub-pixels in a zigzag pattern through a data line. The variation of the feed-through voltages of the sub-pixels may be modified by adjusting the ratios of the channel widths and the channel lengths of the TFTs in the sub-pixels to some predetermined ratios, or by adjusting the compensation capacitance to the coupling capacitance of the TFTs of the sub-pixels.

Abstract: A semiconductor structure of a display device and the method for fabricating the same are provided. The semiconductor structure is formed on a substrate having a TFT region and a pixel capacitor region thereon. A TFT, including a gate electrode, a source electrode, a drain electrode, a channel layer, and a gate insulating layer, is formed on the TFT region of the substrate. A pixel capacitor is formed on the pixel capacitor region, wherein the pixel capacitor comprises a bottom electrode formed on a bottom dielectric layer, an interlayer dielectric layer formed on the bottom electrode, a top electrode formed on the interlayer dielectric layer, a contact plug passing through the interlayer dielectric layer and electrically connected to the top and bottom electrodes, a capacitor dielectric layer formed on the top electrode, a transparent electrode formed on the capacitor dielectric layer and electrically connected to the drain electrode.

Abstract: The invention discloses a method for boosting the downlink transmission rate to a mobile station by a processing unit thereof, including the steps of predicting a total number of acknowledgement (ACK) packets that are going to be generated, wherein the predicted total number of the ACK packets is a fixed value, predicting timing for when the ACK packets will be generated, determining a bandwidth amount according to the predicted total number of the ACK packets, issuing a bandwidth amount request with the determined bandwidth amount from the mobile station to a base station for the ACK packets to be generated and transmitted to the base station before generation of the ACK packets, generating the ACK packets, and instructing an RF module to transmit the ACK packets to the base station following a notification from the base station indicating that the requested bandwidth amount has been allocated.

Abstract: A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.

Abstract: An active array substrate, a liquid crystal display panel and a method for manufacturing the active array substrate are provided. The active array substrate includes a base, scan lines, data lines and gate tracking lines disposed on the base. Each of the gate tracking lines has first portions, auxiliary portions and junction portions, wherein the junction portion and the first portion are formed in different layers. One of the junction portions is electrically connected with corresponding one of the first portions.

Abstract: A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.

Abstract: An active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is disposed on the display area of the substrate. A gate insulator is disposed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are disposed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then disposed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is disposed on the passivation layer.

Abstract: An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a first insulating layer, a pixel electrode, a capacitor electrode, and a second insulating layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The first insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the first insulating layer. The second insulating layer is located between the capacitor electrode and the drain.

Abstract: A photo-voltaic cell device includes a first electrode, an N-type doped silicon-rich dielectric layer, a P-type doped silicon-rich dielectric layer, and a second electrode. The N-type doped silicon-rich dielectric layer is disposed on the first electrode, and the N-type doped silicon-rich dielectric layer is doped with an N-type dopant. The P-type doped silicon-rich dielectric layer is disposed on the N-type doped silicon-rich dielectric layer, and the P-type doped silicon-rich dielectric layer is doped with a P-type dopant. The second electrode is disposed on the P-type doped silicon-rich dielectric layer. A display panel including the photo-voltaic cell device is also provided.

Abstract: A method for fabricating an active device array substrate is provided. First, a substrate having a display area and a sensing area is provided. Then, a first patterned conductor layer is formed on the display area of the substrate. A gate insulator is formed on the substrate. A patterned semiconductor layer, a second patterned conductor layer and a patterned photosensitive dielectric layer are formed on the gate insulator, wherein the second patterned conductor layer includes a source electrode, a drain electrode and a lower electrode, the patterned photosensitive dielectric layer covering the second patterned conductor layer includes an interface protection layer disposed on the source electrode and the drain electrode and a photo-sensing layer disposed on the lower electrode. A passivation layer is then formed on the substrate. After that, a third patterned conductor layer including a pixel electrode and an upper electrode is formed on the passivation layer.

Abstract: A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer.

Abstract: The invention discloses a method for boosting the downlink transmission rate to a mobile station by a processing unit thereof, including the steps of requesting a base station for a bandwidth amount for transmission of at least one un-generated acknowledgement (ACK) packet, generating the ACK packet or packets, and instructing an RF module to transmit the ACK packet or packets to the base station following a notification from the base station indicating that the requested bandwidth amount has been allocated.