Patents by Inventor Yu-Cheng Chen

Yu-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120057090
    Abstract: An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain.
    Type: Application
    Filed: February 18, 2011
    Publication date: March 8, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Yu-Cheng Chen, Yi-Hui Li, Chih-Hung Lin, Maw-Song Chen
  • Publication number: 20120023210
    Abstract: An operation method for a server system includes: (A) under control of a hardware abstraction layer (HAL), a plurality of node management units sharing a hardware resource; (B) if one of the node management units needs to use the hardware resource, the node management unit sending an instruction or a data to the HAL and accordingly the HAL using the hardware resource in represent of the node management unit; and (C) if an external instruction is received, the HAL identifying which transmission port of the hardware resource receives the external instruction, so to send the external instruction to a corresponding node management unit, and after the external instruction is executed, the corresponding node management unit sending back an information to the HAL so that the HAL sends back the information to an external system administrator.
    Type: Application
    Filed: December 3, 2010
    Publication date: January 26, 2012
    Applicant: Quanta Computer Inc.
    Inventors: Te-Hsien LAI, Yu-Cheng Chen, Ching-Fu Kung
  • Patent number: 8072566
    Abstract: A method of forming a transflective LCD panel is provided. The transflective LCD includes a substrate, a first polycrystalline silicon pattern disposed in a reflection region, a second polycrystalline silicon pattern disposed in a peripheral region, an insulating layer disposed on the first and second polycrystalline silicon pattern and the substrate, a gate electrode disposed in the reflection region, a common electrode disposed in the peripheral region, a first inter-layer dielectric disposed on the insulating layer, the gate electrode and the common electrode, a reflection electrode disposed on the first inter-layer dielectric, a second inter-layer dielectric disposed on the first inter-layer dielectric and the reflection electrode, and a transmission electrode disposed on the second inter-layer dielectric and electrically connected to the reflection electrode through an opening of the second inter-layer dielectric.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: December 6, 2011
    Assignee: AU Optronics Corp.
    Inventors: Yu-Cheng Chen, Tun-Chun Yang
  • Publication number: 20110292331
    Abstract: A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line.
    Type: Application
    Filed: October 22, 2010
    Publication date: December 1, 2011
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Ke-Chih Chang, Kuo-Yu Huang, Yu-Cheng Chen, Tsan-Chun Wang
  • Publication number: 20110273654
    Abstract: An active device array substrate includes a substrate, scan lines disposed on the substrate, data lines intersected with the scan lines, scan signal transmission lines, and pixel units. The scan signal transmission lines are intersected with the scan lines. Each scan signal transmission line connects one scan line through a node. The pixel unit electrically connects the corresponding data line and the corresponding scan line and includes an active device and a pixel electrode. The active device has a gate, a source, and a drain. The pixel electrode electrically connects the drain. In the pixel units not adjacent to the nodes, a gate-to-drain capacitance of each active device is Cgd1. In the pixel units adjacent to the nodes, the gate-to-drain capacitances of some active devices are Cgd2, the gate-to-drain capacitances of the other active devices are Cgd1, and Cgd1?Cgd2.
    Type: Application
    Filed: June 14, 2010
    Publication date: November 10, 2011
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Tsan-Chun Wang, Yu-Cheng Chen
  • Patent number: 8035782
    Abstract: A transflective LCD panel includes a substrate, a first polycrystalline silicon pattern disposed in a reflection region, a second polycrystalline silicon pattern disposed in a peripheral region, an insulating layer disposed on the first and second polycrystalline silicon pattern and the substrate, a gate electrode disposed on the insulating layer in the reflection region, a storage capacitor line disposed on the insulating layer in the peripheral region, a first inter-layer dielectric disposed on the insulating layer, the gate electrode and the storage capacitor line, a reflection electrode disposed on the first inter-layer dielectric, a second inter-layer dielectric disposed on the first inter-layer dielectric and the reflection electrode, and a transmission electrode disposed on the second inter-layer dielectric and electrically connected to the reflection electrode through an opening of the second inter-layer dielectric.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: October 11, 2011
    Assignee: AU Optronics Corp.
    Inventors: Yu-Cheng Chen, Tun-Chun Yang
  • Patent number: 8032766
    Abstract: A machine boot up protection structure for parallel power supply equipment provides a determination level to set the parallel power supply equipment in an ON condition. It has a control unit to receive a connection signal output by each of power supply units to compare with the determination level. If the comparison matches, all of the power supply units are activated to the ON condition. If the comparison does not match, all of the power supply units are set to an OFF condition. Thereby when the external power is not completely connected, some of the power supply units do not suffer from overloading and damaging.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: October 4, 2011
    Assignee: Zippy Technology Corp.
    Inventors: Tsung-Chun Chen, Yu-Cheng Chen
  • Publication number: 20110233567
    Abstract: A pixel array is located on a substrate and includes a plurality of pixel sets. Each of the pixel sets includes a first scan line, a second scan line, a data line, a data signal transmission line, a first pixel unit, and a second pixel unit. The data line is not parallel to the first and the second scan lines. The data signal transmission line is disposed parallel to the first and the second scan lines and electrically connected to the data line. Distance between the first and the second scan lines is smaller than distance between the data signal transmission line and one of the first and the second scan lines. The first pixel unit is electrically connected to the first scan line and the data line. The second pixel unit is electrically connected to the second scan line and the data line.
    Type: Application
    Filed: May 27, 2010
    Publication date: September 29, 2011
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Yi-Hui Li, Yu-Cheng Chen, Tsan-Chun Wang, Chih-Hung Lin, Tung-Huang Chen
  • Publication number: 20110196951
    Abstract: A computer managing method includes the following steps. Firstly, a blade server system with M blade server units, which includes a number of server blades and a modular management blade (MMB), is provided, wherein the M MMBs are connected with each other via network paths and M is a natural number greater than 1. Then a master MMB among the M MMBs are selected in response to first user operation event. Next, the network parameter data of the master MMB are set in response to second user operation event. Then network topology of the master MMB and the rest of M?1 MMBs are obtained via the master MMB. After that, the rest of M?1 MMBs are driven for utilizing a network protocol service so that the M?1 MMBs are able to receive network parameter data from the master MMB and carry out parameter setting accordingly.
    Type: Application
    Filed: July 27, 2010
    Publication date: August 11, 2011
    Applicant: Quanta Computer Inc.
    Inventors: Che-Hung Chen, Yu-Cheng Chen, Tsun-Li Hung, Shang-Feng Chiang, Chih-Chien Hsu
  • Patent number: 7982807
    Abstract: A method for processing an image includes inputting an image, generating a first mean luminance value and a second mean luminance value according to a plurality of pixels within a first luminance interval and a second luminance interval of the image, generating a first luminance threshold according to the first mean luminance value, setting a compensation parameter, generating a first compensation luminance value according to the first mean luminance value and the compensation parameter, generating a second compensation luminance value according to the first luminance threshold, the first mean luminance value, the second mean luminance value, and the compensation parameter, and adjusting luminance values of pixels within the a smaller compensation luminance value and a greater compensation luminance value according to the smaller compensation value and a comparison between the first compensation luminance value and the second compensation luminance value.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: July 19, 2011
    Assignee: Qisda Corporation
    Inventor: Yu-Cheng Chen
  • Publication number: 20110169787
    Abstract: An exemplary display device includes multiple pixels, first through third gate lines and a data line. The pixels include first through third pixels. The first through third gate lines respectively are electrically coupled with the first through third pixels and for deciding whether to enable the first through third pixels. The first pixel is electrically coupled to the data line to receive a display data provided by the data line. The second pixel is electrically coupled to the first pixel to receive a display data provided by the data line through the first pixel. The third pixel is electrically coupled to the second pixel to receive a display data provided by the data line through both the first pixel and the second pixel. A display driving method adapted to be implemented in the display device also is provided.
    Type: Application
    Filed: January 9, 2010
    Publication date: July 14, 2011
    Inventors: Yu-Cheng CHEN, Yi-Chen CHIANG, Chun-Ting LIU
  • Publication number: 20110165742
    Abstract: A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 7, 2011
    Applicant: AU OPTRONICS CORPORATION
    Inventor: Yu-Cheng Chen
  • Patent number: 7973317
    Abstract: A method for fabricating an array substrate for a liquid crystal display (LCD) is provided. A semiconductor layer and a transparent lower electrode formed on a substrate is provided and covered by a first dielectric layer serving as a gate dielectric layer and a capacitor dielectric layer. A gate electrode and an upper electrode comprising a transparent electrode portion and a metal electrode portion are formed on the first dielectric layer and covered by a second dielectric layer. A source/drain electrode, a planarization layer, and a pixel electrode are sequentially formed on the second dielectric layer, in which the source/drain electrode is electrically connected to the semiconductor layer through the first and second dielectric layers and the pixel electrode is electrically connected to the source/drain electrode through the planarization layer. An array substrate for an LCD is also disclosed.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: July 5, 2011
    Assignee: Au Optronics Corp.
    Inventors: Yu-Cheng Chen, Chen-Yueh Li
  • Publication number: 20110156038
    Abstract: An active device array substrate including a substrate, scan lines, data lines, active devices, a first dielectric layer, a common line, a second dielectric layer, a patterned conductive layer, a third dielectric layer, and pixel electrodes is provided. At least a part of the active devices are electrically connected to the scan lines and the data lines. The first dielectric layer covers the scan lines, the data lines and the active devices. The common line is disposed on the first dielectric layer. The second dielectric layer covers the common line and the first dielectric layer. The patterned conductive layer is disposed on the second dielectric layer. The third dielectric layer covers the patterned conductive layer and the second dielectric layer. The pixel electrodes are disposed on the third dielectric layer and electrically connected to the patterned conductive layer and the active devices.
    Type: Application
    Filed: April 30, 2010
    Publication date: June 30, 2011
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Ching-Jung Yang, Ke-Chih Chang, Kuo-Yu Huang, Yu-Cheng Chen
  • Patent number: 7960731
    Abstract: A multi-layered complementary conductive line structure, a manufacturing method thereof and a manufacturing method of a TFT (thin film transistor) display array are provided. The process of TFT having multi-layered complementary conductive line structures does not need to increase the mask number in comparison with the currently process and is able to solve the resistance problem of the lines inside a display.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: June 14, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Cheng Chen, Chi-Lin Chen, Chi-Ming Chang
  • Publication number: 20110122052
    Abstract: A display device includes a plurality of gate lines, data lines, first external gate tracking lines, and second external gate tracking lines. The first external gate tracking lines are substantially disposed in a border region of a substrate, and electrically connected with corresponding gate lines. The second external gate tracking lines are substantially disposed in the border region of the substrate, and electrically connected with corresponding gate lines. One of the first external gate tracking lines and a corresponding second external gate tracking line at least partially overlap with each other.
    Type: Application
    Filed: April 14, 2010
    Publication date: May 26, 2011
    Inventors: Yu-Cheng Chen, Tsan-Chun Wang, Wan-Yu Lo
  • Patent number: 7939828
    Abstract: A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: May 10, 2011
    Assignee: Au Optronics Corporation
    Inventor: Yu-Cheng Chen
  • Patent number: 7939964
    Abstract: A modularized power supply switch control structure aims to control a main power system of a power supply. The main power system includes at least one high voltage output unit at a high voltage output end and one low voltage output unit at a rear low voltage output end. A control unit is connected to the high voltage output unit and the low voltage output unit to control start/stop time series of the high voltage output unit and the low voltage output unit so that the high voltage output unit and the low voltage output unit can be started asynchronously. Thus the power supply can output a start voltage at the start instant to meet load requirement. A plurality of power output modules deliver output asynchronously. Hence output current or voltage surge at the start instant can be improved.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: May 10, 2011
    Assignee: Zippy Technology Corp.
    Inventor: Yu-Cheng Chen
  • Patent number: 7927929
    Abstract: A method of fabricating a thin film transistor (TFT) includes first providing a strip-shaped silicon island which is a thin film region with a predetermined long side and short side. Next, the strip-shaped silicon island is subject to an ion implantation to form a first ion doping region and a second ion doping region. The first and second ion doping regions, respectively used as the source and the drain of the TFT, are located at two sides along the long side of the island and substantially perpendicular to the gate. A gate is formed over the strip-shaped silicon island and the first and second ion doping regions, wherein the gate is substantially parallel to the direction of the short side.
    Type: Grant
    Filed: February 16, 2009
    Date of Patent: April 19, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chi-Lin Chen, Yu-Cheng Chen, Hsing-Hua Wu, Po-Tsun Liu
  • Publication number: 20110080388
    Abstract: A display panel including an active device array substrate, an opposite substrate and a display medium is provided. The active device array substrate includes a substrate, scan lines, data lines, pixel units, and data signal transmission lines. The scan lines and data lines define a plurality of pixel regions on the substrate. Each pixel unit is disposed within one of the pixel regions respectively, and each pixel unit includes a plurality of sub-pixel units. The sub-pixel units within the same pixel unit are electrically connected with the same data line, and each sub-pixel unit within the same pixel unit is electrically connected with one of the scan lines respectively. Each data signal transmission line is electrically connected with one of the data lines, and an extending direction of the data signal transmission line is substantially parallel with an extending direction of the scan lines.
    Type: Application
    Filed: December 3, 2009
    Publication date: April 7, 2011
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Wan-Yu Lo, Tsan-Chun Wang, Yu-Cheng Chen, Maw-Song Chen