Abstract: The present disclosure relates to a semiconductor device and a fabricating method thereof, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: A semiconductor structure is provided in the present invention, including a substrate with multiple recesses and active areas, multiple bit lines spaced apart in a first direction on the cell region and extending in a second direction perpendicular to the first direction, and the bit line is electrically connected to an active area in the substrate through the recess, and a dummy bit line at an outermost side of the multiple bit lines in the first direction and extending in the second direction, wherein a width of the dummy bit line in the first direction is larger than a width of the bit line in the first direction, and the bit lines and the dummy bit line have the same composition and layer structures.

Abstract: A method of manufacturing a semiconductor memory device is provided in the present invention, including steps of providing a substrate, forming word lines extending in a first direction in said substrate, forming bit lines extending in a second direction over said word lines, forming partition structures between said bit lines and right above said word lines, forming storage node contacts in spaces defined by said bit lines and said partition structures, wherein a portion of said storage node contact protruding from top surfaces of said bit lines and said partition structures is contact pad, forming a silicon nitride liner on said contact pads, said bit lines and said partition structures, and forming a silicon oxide layer on said silicon nitride liner.

Abstract: A semiconductor device includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.

Abstract: The present disclosure relates to a semiconductor memory device and a method of fabricating the same, and the semiconductor memory device includes a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate and includes a first active region and a second active region. The first active region includes a plurality of active region units, and the second active region is disposed at an outer side of the first active region to directly connect to a portion of the active region units. The second active region includes a plurality of first openings disposed an edge of the second active region. The shallow trench isolation is disposed within the substrate, to surround the active structure.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: The present disclosure relates to a semiconductor memory device including a substrate, a plurality of buried word lines, a plurality of bit lines, and a plurality isolation fins. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are disposed in the substrate. The bit lines are disposed on the substrate. The isolation fins are disposed on the substrate, over each of the buried word lines respectively, wherein a portion of the isolation fins is disposed under the bit lines and overlapped with the bit lines.

Abstract: The present disclosure relates to a semiconductor memory device and a fabricating method thereof, includes a substrate, a plurality of gate structures, a plurality of isolation fins, at least one bit line, and a plug. The gate structures are disposed in the substrate, being parallel with each other along a first direction. The isolation fins are disposed on the substrate, parallel with each other and extending along the first direction, over each of the gate structures respectively. The bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The bit line includes a plurality of pins extending toward the substrate, being alternately arranged with the isolation fins along the second direction. The plug is disposed on the substrate, being alternately with the bit line in the first direction.

Abstract: The present invention provides a manufacturing method of a semiconductor device and a semiconductor device. A semiconductor device is provided, the semiconductor device includes a substrate, a stacked structure disposed on the substrate, the substrate comprises a cell array region, a peripheral circuit region and a middle region between the cell array region and the peripheral circuit region, the stacked structure comprises a first support layer, a first trench located in the middle region, a second support layer located on an upper surface of the stacked structure, wherein parts of the second support layer is disposed in the first trench, a portion of a sidewall of the first support layer directly contacts a portion of a sidewall of the second support layer, and a capacitor structure located in the cell array region.

Abstract: A semiconductor memory device is provided in the present invention, including a substrate, word lines in the substrate, bit lines over the word lines, partition structures between the bit lines and right above the word lines, storage node contacts in spaces defined by the bit lines and the partition structures and electrically connecting with the substrate, wherein a portion of the storage node contact protruding from top surfaces of the bit lines and the partition structures is contact pad, and contact pad isolation structures on the partition structures and between the contact pads, wherein the contact pad isolation structure includes outer silicon nitride layers and inner silicon oxide layers.

Abstract: A layout of a semiconductor device and a method of forming a semiconductor device, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.

Abstract: The present disclosure relates to a semiconductor memory device and a fabricating method thereof, and the semiconductor memory device includes a substrate, bit lines, plugs and a spacer structure. The bit lines are separately disposed on the substrate, and the plugs are also disposed on the substrate to alternately arrange with the bit lines. The spacer structure is disposed on the substrate, between each of the bit lines and each of the plugs. The spacer structure includes a first air gap layer, a first spacer and a second air gap layer, and the first air gap layer, the first spacer and the second air gap layer are sequentially stacked between sidewalls of the bit lines and the plugs. Therefore, two air gap layers may be formed between the bit lines and the storage node contacts to improve the delay between the resistor and the capacitor.

Abstract: A capacitor structure and a manufacturing method thereof are disclosed in this invention. The capacitor structure includes a first electrode, a second electrode, and a capacitor dielectric stacked layer. The capacitor dielectric stacked layer is disposed between the first electrode and the second electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. A manufacturing method of a capacitor structure includes the following steps. A capacitor dielectric stacked layer is formed on a first electrode, and the capacitor dielectric stacked layer includes a first dielectric layer. The first dielectric layer includes a first zirconium oxide layer and a first zirconium silicon oxide layer. Subsequently, a second electrode is formed on the capacitor dielectric stacked layer, and the capacitor dielectric stacked layer is located between the first electrode and the second electrode.

Abstract: The present invention provides a semiconductor memory device including a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.

Abstract: A semiconductor memory device includes a substrate, at least one word line, a plurality of bit lines and a plurality of insulating structures. The word line is disposed in the substrate, extends along a first direction, and includes a gate cap layer. The bit lines are disposed on the substrate and respectively extend along a second direction. The bit line crosses the word line, and includes a conductive layer. The insulating structures are disposed on the word line and respectively disposed between the bit lines. The bottom surface of the insulating structure is located in the gate cap layer. The area of the top surface of the insulating structure is larger than the area of the bottom surface of the insulating structure.

Abstract: The invention provides a semiconductor storage device including a substrate, a plurality of active areas which are arranged along an oblique direction, a dummy active area pattern, and the dummy active area pattern comprises a first edge principal axis pattern and a plurality of first long branches and a plurality of short branches connecting edge principal axis patterns, and a plurality of storage nodes are in contact with each other. According to the invention, a part of the storage node contacts are arranged on the dummy active area pattern, so that the difficulty of the manufacturing process can be reduced, and the surrounding storage node contacts can serve as protection structures to protect components and prevent the components from being physically or electrically affected.

Abstract: The present disclosure relates to a fabricating method of a semiconductor memory device including the following steps. Firstly, a substrate is provided, and a plurality of gate structures is formed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. Next, a plurality of isolation fins is formed on the substrate, wherein each of the isolation fins is parallel with each other and extends along the first direction, over each of the gate structures respectively. After forming the isolation fins, at least one bit line is formed on the substrate, extending along a second direction being perpendicular to the first direction, wherein the at least one bit line comprises a plurality of pins extending along a direction being perpendicular to the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.

Abstract: A semiconductor structure, including a plurality of connection patterns disposed on the substrate, and a merged pattern disposed between adjacent two of the connection patterns, wherein the merged pattern includes a first outer line, a central line and a second outer line sequentially arranged along a first direction and connected with each other, and an end surface of the first outer line, an end surface of the central line and an end surface of the second outer line are misaligned along the first direction.

Abstract: A semiconductor memory device includes a substrate, an active structure, a shallow trench isolation and a plurality of word lines. The active structure is disposed in the substrate, and includes a plurality of first active fragments and a plurality of second active fragments extended parallel to each other along a first direction and the second active fragments are disposed outside a periphery of all of the first active fragments. The shallow trench isolation is disposed in the substrate to surround the active structure, and which includes a plurality of first portions and a plurality of second portions. The word lines are disposed in the substrate, parallel with each other to extend along a second direction, wherein at least one of the word lines are only intersected with the second active fragments, or at least one of the word lines does not pass through any one of the second portions.