Abstract: A pixel structure includes a first conductive layer, a semiconductor layer, an insulating layer, a second conductive layer, a passivation layer, and a first electrode layer. The first conductive layer includes a scan line and a bottom electrode. The semiconductor layer includes a first semiconductor pattern having a first source region, a first drain region, and a first channel region. The insulating layer is disposed on the semiconductor layer. The second conductive layer is disposed on the insulating layer and includes a top electrode, a first gate, a first source, a first drain, and a data line connected with the first source. The bottom electrode and the top electrode overlap to form a capacitor. The passivation layer covers the first and second conductive layers and the semiconductor layer. The first electrode layer is disposed on the passivation layer and provides electrical connection to different layers.

Abstract: A pixel structure includes a first conductive layer, a semiconductor layer, an insulating layer, a second conductive layer, a passivation layer, and a first electrode layer. The first conductive layer includes a scan line and a bottom electrode. The semiconductor layer includes a first semiconductor pattern having a first source region, a first drain region, and a first channel region. The insulating layer is disposed on the semiconductor layer. The second conductive layer is disposed on the insulating layer and includes a top electrode, a first gate, a first source, a first drain, and a data line connected with the first source. The bottom electrode and the top electrode overlap to form a capacitor. The passivation layer covers the first and second conductive layers and the semiconductor layer. The first electrode layer is disposed on the passivation layer and provides electrical connection to different layers.

Abstract: A pixel structure includes a semiconductor layer, an insulating layer, a first conductive layer, a second conductive layer, a passivation layer, and a first electrode layer. The semiconductor layer includes a first semiconductor pattern having a first source region, a first drain region, and a first channel region. The insulating layer is disposed on the semiconductor layer. The first conductive layer is disposed on the insulating layer and includes a first gate, a first source, a first drain, and a data line connected to the first source. The second conductive layer is disposed on the first conductive layer and includes a scan line. The passivation layer covers the first and second conductive layers and the semiconductor layer. The first electrode layer is disposed on the passivation layer and provides electrical connection to different layers.

Abstract: A method of manufacturing a substrate is disclosed. The method includes receiving a plurality of pixel elements, wherein each of the pixel elements includes data members; and transferring the data members to a plurality of exposing devices that are configured to conditionally expose the substrate with an incident energy beam when coupled with the data members, wherein different data members of one pixel element are transferred at different system cycles.

Abstract: A thin-film transistor includes a gate electrode, a capacitance compensation structure, a semiconductor layer, a dielectric layer, a drain electrode and a source electrode. The capacitance compensation structure is disposed on the substrate and electrically connected to the gate electrode. The capacitance compensation structure has a first side facing the gate electrode and a second side facing away from the gate electrode. The semiconductor layer covers a portion of the gate electrode, and at least extends to overlap the first side of the capacitance compensation structure. The dielectric layer has a first opening and a second opening. Both of the first opening and the second opening expose a portion of the semiconductor layer overlapping the gate electrode respectively. The drain electrode is in contact with the semiconductor layer though the first opening. The source electrode is in contact with the semiconductor layer though the second opening.

Abstract: A method of manufacturing a wafer with an integrated circuit (IC) layout includes receiving a first plurality of pixels, wherein each of the pixels corresponds to a portion of the IC layout and includes data members. The method further includes transforming the first plurality of pixels into a second plurality of control signals, wherein at least some of the control signals include both a data member of one of the pixels and another data member of another one of the pixels. The method further includes transferring the control signals to a third plurality of mirrors, wherein the mirrors conditionally reflect an energy beam incident thereupon when coupled with the control signals.

Abstract: A system using an energy beam to expose patterns on a wafer includes first mirror elements, a multiplexer element, and second mirror elements. The first and second mirror elements are dynamically controlled to reflect the energy beam to the wafer. The first mirror elements are configured in a first chain having a first data input and a first data output. The multiplexer element includes a second data input, a third data input, a select input, and a second data output. The third data input is coupled to the first data output. The second mirror elements are configured in a second chain having a fourth data input.

Abstract: An electroluminescent display panel and method of fabricating the same are provided. The electroluminescent display panel includes a first multiple-layered structural layer, a second multiple-layered structural layer, a passivation layer and a third patterned conductive layer. The first multiple-layered structural layer includes a first patterned conductive layer, a first patterned insulation layer and an oxide semiconductor layer, and the first patterned conductive layer, the first patterned insulation layer and the oxide semiconductor layer have substantially the same shape. The second multiple-layered structural layer includes a second patterned conductive layer. The passivation layer has a plurality of through holes. A portion of the through holes expose the top surface and the lateral surface of the oxide semiconductor layer and the lateral surface of the first patterned conductive layer.

Abstract: A thin-film transistor includes a gate electrode, a capacitance compensation structure, a semiconductor layer, a dielectric layer, a drain electrode and a source electrode. The capacitance compensation structure is disposed on the substrate and electrically connected to the gate electrode. The capacitance compensation structure has a first side facing the gate electrode and a second side facing away from the gate electrode. The semiconductor layer covers a portion of the gate electrode, and at least extends to overlap the first side of the capacitance compensation structure. The dielectric layer has a first opening and a second opening. Both of the first opening and the second opening expose a portion of the semiconductor layer overlapping the gate electrode respectively. The drain electrode is in contact with the semiconductor layer though the first opening. The source electrode is in contact with the semiconductor layer though the second opening.

Abstract: An electroluminescent display panel and method of fabricating the same are provided. The electroluminescent display panel includes a first multiple-layered structural layer, a second multiple-layered structural layer, a passivation layer and a third patterned conductive layer. The first multiple-layered structural layer includes a first patterned conductive layer, a first patterned insulation layer and an oxide semiconductor layer, and the first patterned conductive layer, the first patterned insulation layer and the oxide semiconductor layer have substantially the same shape. The second multiple-layered structural layer includes a second patterned conductive layer. The passivation layer has a plurality of through holes. A portion of the through holes expose the top surface and the lateral surface of the oxide semiconductor layer and the lateral surface of the first patterned conductive layer.

Abstract: An electret loudspeaker device including a diaphragm, a first perforated electrode and a first spacer is provided. The diaphragm includes a first electret, a second electret, a polymer layer and an electrode layer. At least one layer of the first electret or the second electret is formed by expanded polytetrafluoroethylene. The second electret is stacked on one side of the first electret, while the electrode layer is stacked on the opposite side of the first electret. The polymer layer is made of a hydrophobic material and is disposed on the second electret. The first perforated electrode is stacked on a first spacer and close to the polymer layer. The first spacer disposed between the diaphragm and the first perforated electrode supports the first perforated electrode over the diaphragm and defines a first chamber. A fabrication method of the electret loudspeaker device is also provided.

Abstract: A pixel structure including a first thin film transistor (TFT), a second TFT and a storage capacitor is provided. The source electrode of the first TFT is connected to the gate electrode of the second TFT, and the semiconductor layer of the second TFT protrudes out two opposite side of the gate electrode of the second TFT. A thin film transistor including a gate electrode, a capacitance compensation structure, a semiconductor layer, a dielectric layer, a drain electrode and a source electrode is also provided. The capacitance compensation structure is electrically connected to the gate electrode. The semiconductor layer partially overlaps the gate electrode, and extends to overlap the capacitance compensation structure.

Abstract: An electret loudspeaker device including a diaphragm, a first perforated electrode and a first spacer is provided. The diaphragm has an electret layer and an electrode layer. The first perforated electrode is stacked on a side of the diaphragm near the electret layer, and has multiple holes. The first spacer is stacked between the diaphragm and the first perforated electrode, and includes a first distribution area and plural second distribution areas. The first distribution area has first openings penetrating through the first spacer, and each first opening has a first opening space volume between the diaphragm and the first perforated electrode. Each second distribution area has second openings penetrating through the first spacer, and each second opening has a second opening space volume between the diaphragm and the first perforated electrode. A difference between the first and the second opening space volumes is greater than 10%.

Abstract: A pixel structure including a first thin film transistor (TFT), a second TFT and a storage capacitor is provided. The source electrode of the first TFT is connected to the gate electrode of the second TFT, and the semiconductor layer of the second TFT protrudes out two opposite side of the gate electrode of the second TFT. A thin film transistor including a gate electrode, a capacitance compensation structure, a semiconductor layer, a dielectric layer, a drain electrode and a source electrode is also provided. The capacitance compensation structure is electrically connected to the gate electrode. The semiconductor layer partially overlaps the gate electrode, and extends to overlap the capacitance compensation structure.

Abstract: A luggage includes a main body. The main body includes a foamed plastic layer and a thin film layer coated on the foamed plastic layer. Thus, the foamed plastic layer is shockproof, shatterproof, chemical resistant and impact-resistant so that the main body of the luggage is not easily broken or worn out during a long-term utilization. In addition, the foamed plastic layer has a lighter weight so that the main body of the luggage is carried easily and conveniently. Further, the thin film layer is coated on the foamed plastic layer to protect the foamed plastic layer. Further, the thin film layer surrounds the inner surface of the foamed plastic layer and is provided with streaks or patterns so as to enhance the aesthetic quality of the foamed plastic layer.

Abstract: A clock and data recovery (CDR) circuit includes an edge detector, an edge selector, and a phase selector. The edge detector is arranged to detect edges of serial input data and to provide an edge detection result. The serial input data is oversampled utilizing multiple clock phases. The edge selector for selecting one of the multiple clock phases for a recovered clock is arranged to provide an edge selection result, to receive the last edge selection result as a first input, and to receive the edge detection result as a second input. The phase selector is arranged to provide the recovered clock and recovered data.

Abstract: A method for progressive JPEG image decoding and a method for controlling a decoder are disclosed. In the image decoding method, an amount of macroblocks that can be stored during the process of decoding is determined according to the size of the memory, and then, according to the amount of macroblocks, a scan layer is divided into a plurality of decoding areas. In each turn of decoding, data of the same decoding area in all the scan layers are decoded. In the next turn, a decoding area next to the previous one is selected for decoding. Therefore, the present invention can decode the image correctly with a limited memory resource, without affecting the display quality of the image. The image decoding method also can be applied to the control of a decoder, so as to reduce the occupied memory capacity.

Abstract: A progressive JPEG image decoding method is provided. In the decoding method, a non-zero history table and a sign table of each variable length decoding (VLD) result are recorded and used as a reference for decoding the next scan layer. The decoded coefficients are no longer directly stored in a memory so as to save the memory space. Accordingly, an image can be decoded and displayed correctly even with limited memory space.

Abstract: An electret loudspeaker device including a diaphragm, a first perforated electrode and a first spacer is provided. The diaphragm has an electret layer and an electrode layer. The first perforated electrode is stacked on a side of the diaphragm near the electret layer, and has multiple holes. The first spacer is stacked between the diaphragm and the first perforated electrode, and includes a first distribution area and plural second distribution areas. The first distribution area has first openings penetrating through the first spacer, and each first opening has a first opening space volume between the diaphragm and the first perforated electrode. Each second distribution area has second openings penetrating through the first spacer, and each second opening has a second opening space volume between the diaphragm and the first perforated electrode. A difference between the first and the second opening space volumes is greater than 10%.

Abstract: An electret loudspeaker device including a diaphragm, a first perforated electrode and a first spacer is provided. The diaphragm includes a first electret, a second electret, a polymer layer and an electrode layer. At least one layer of the first electret or the second electret is formed by expanded polytetrafluoroethylene. The second electret is stacked on one side of the first electret, while the electrode layer is stacked on the opposite side of the first electret. The polymer layer is made of a hydrophobic material and is disposed on the second electret. The first perforated electrode is stacked on a first spacer and close to the polymer layer. The first spacer disposed to between the diaphragm and the first perforated electrode supports the first perforated electrode over the diaphragm and defines a first chamber. A fabrication method of the electret loudspeaker device is also provided.