Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.

Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.

Abstract: A radio frequency (RF) phased-array detector includes a vertical antenna array, a horizontal antenna array, a multiplexer module and a processor. The vertical antenna array includes a plurality of vertical antennas, and each of the vertical antennas is configured to obtain a first input signal in response to a wireless signal from a radio-emitting source. The horizontal antenna array includes a plurality of horizontal antennas, and each of the horizontal antennas is configured to obtain a second input signal in response to the wireless signal. The multiplexer module is configured to provide a plurality of third input signals selected from the first input signals and the second input signals. The processor is configured to obtain azimuth and elevation of the radio-emitting source according to the third input signals.

Abstract: A radar system includes a first subarray, a second subarray and a third subarray. The first subarray includes a plurality of first antennas arranged along a first direction. The second subarray includes a plurality of second antennas arranged along the first direction. The third subarray includes a plurality of third antennas arranged along a second direction orthogonal to the first direction. The third subarray is configured to combine a first set of data received from the first subarray and a second set of data received from the second subarray into a combined set of data, generate first beamformed data indicating target azimuth information by applying beamforming to the combined set of data, and generate second beamformed data indicating target elevation information according to a plurality of input signals received by the third antennas.

Abstract: A monolithic array chip comprises a first semiconductor layer; a common electrode located on the first semiconductor layer; a first light-emitting unit with a first electrode located on the first semiconductor layer; a second light-emitting unit with a second electrode located on the first semiconductor layer; a third light-emitting unit with a third electrode located on the first semiconductor layer, wherein the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are separated from each other by a trench.

Abstract: Provided is a method for preparing a tissue section, including treating a tissue specimen with a clearing agent and at least one labeling agent to obtain a cleared and labeled tissue specimen; generating a three-dimensional (3D) image of the cleared and labeled tissue specimen; performing an image slicing procedure on the 3D image to generate a plurality of two-dimensional (2D) images; identifying a target 2D image among the plurality of 2D images to obtain a distance value of D1, which indicates the distance between the target 2D image and a predetermined surface of the 3D image; preparing a hardened tissue specimen from the cleared and labeled tissue specimen; and cutting the hardened tissue specimen near a predetermined site to obtain a tissue section, wherein the distance between the predetermined site and a surface of the hardened tissue specimen corresponding to the predetermined surface of the 3D image is D1.

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Abstract: An electronic package and a manufacturing method thereof are provided, in which a heat sink with an opening is disposed on an electronic component of a carrier structure, a heat dissipation material is formed in the opening, and a heat dissipation lid is disposed on the opening to cover the heat dissipation material, such that the problem of insufficient heat dissipation due to the loss of the heat dissipation material can be prevented from occurring to the electronic component.

Abstract: A light-conversion material and a light-emitting device and a display device including the same are provided. The light-conversion material is represented by formula (I): MmDdAaCcEeGg:Rr (I). Wherein M is Ca, Sr, or Ba; D is Zn, Cd, or a combination thereof; A is B, Al, or Ga; C is Si; E is O, S, or Se; G is N, P, As, Sb, or Bi; and R is Eu, Sm, or Yb. The formula (I) is satisfied by 0.5?m?2; 1?d?4; 0?a?2; 0.1?c?3.5; 0.1?e?4; 0.5?g?5.5; and 0.1?r?1.

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: The present application discloses a radar system. The radar system includes a first subarray, a second subarray, and a third subarray. Antennas in the first subarray and the second subarray are disposed along a first axis, and antennas in the third subarray are disposed along a second axis. When scanning a radar coverage of the radar system, the radar system utilizes the first subarray and the second subarray as RF signal transceivers and utilizes the third subarray as a RF signal receiver to scan a first detection distance range according to first signal parameters and scan a second detection distance range according to second signal parameters. A maximum distance measured from the radar system to each detectable location in the first detection distance range is less than or equal to a minimum distance measured from the radar system to each detectable location in the second detection distance range.

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

Abstract: A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material contacting a first word line; an oxide semiconductor (OS) layer contacting a source line and a bit line, the FE material being disposed between the OS layer and the first word line; a dielectric material contacting the FE material, the FE material being between the dielectric material and the first word line; an inter-metal dielectric (IMD) over the first word line; a first contact extending through the IMD to the first word line, the first contact being electrically coupled to the first word line; a second contact extending through the dielectric material and the FE material; and a first conductive line electrically coupling the first contact to the second contact.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a gate spacer layer formed on a sidewall surface of the gate structure. The semiconductor structure includes a source/drain (S/D) epitaxial layer formed adjacent to the gate structure, and a dielectric spacer layer formed on the S/D epitaxial layer. The semiconductor structure includes a contact plug barrier formed over the S/D epitaxial layer, and a contact plug surrounding by the contact plug barrier, wherein the contact plug is separated from the gate spacer layer by the dielectric spacer layer and the contact plug barrier.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric (ILD) layer around the spacer, performing a plasma treatment process to transform the spacer into a first bottom portion and a first top portion, performing a cleaning process to remove the first top portion, and forming a second ILD layer on the metal gate and the first ILD layer.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.