Patents by Inventor Yu-feng Chen

Yu-feng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200135664
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 30, 2020
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Publication number: 20200126599
    Abstract: Memory devices may have internal circuitry that employs voltages higher than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate, internally, higher voltages for operation. The number of available charge pumps in a memory device may be higher than the number used for certain memory operations. Gating circuitry may be used to selectively enable charge pump cores based on power demands that may be associated with a mode of operation and/or a command.
    Type: Application
    Filed: July 5, 2019
    Publication date: April 23, 2020
    Inventors: Harish N. Venkata, Yu-Feng Chen
  • Publication number: 20200117874
    Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yu-Feng Chen, Chih-Hua Chen, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 10622031
    Abstract: Memory devices may have internal circuitry that employs voltages higher than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate, internally, higher voltages for operation. The number of available charge pumps in a memory device may be higher than the number used for certain memory operations. Gating circuitry may be used to selectively enable charge pump cores based on power demands that may be associated with a mode of operation and/or a command.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Harish N. Venkata, Yu-Feng Chen
  • Publication number: 20200105696
    Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.
    Type: Application
    Filed: July 1, 2019
    Publication date: April 2, 2020
    Inventors: Ming-Da Cheng, Yung-Ching Chao, Chun Kai Tzeng, Lin Cheng Jen, Kang Chin Wei, Yu-Feng Chen, Mirng-Ji Lii
  • Publication number: 20200058601
    Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Yu-Feng Chen, Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
  • Patent number: 10553561
    Abstract: A method of forming a semiconductor device includes preparing a first semiconductor die package with conductive elements embedded in a molding compound, wherein the conductive elements are exposed on a surface of the molding compound. A top surface of the conductive elements is above or co-planar with a top-most surface of the molding compound. The method further includes providing a second semiconductor die package; and bonding the conductive elements of the first semiconductor die package to contacts on the semiconductor die package.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Feng Chen, Chun-Hung Lin, Han-Ping Pu, Ming-Da Cheng, Kai-Chiang Wu
  • Publication number: 20190392887
    Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 26, 2019
    Inventors: Yu-Feng Chen, Byung S. Moon, Myung Ho Bae, Harish N. Venkata
  • Patent number: 10509938
    Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yu-Feng Chen, Chih-Hua Chen, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 10504856
    Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Chen, Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
  • Patent number: 10497424
    Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yu-Feng Chen, Byung S. Moon, Myung Ho Bae, Harish N. Venkata
  • Publication number: 20190340405
    Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: Chih-Hua Chen, Yu-Feng Chen, Chung-Shi Liu, Chen-Hua Yu, Hao-Yi Tsai, Yu-Chih Huang
  • Publication number: 20190333594
    Abstract: An electronic device including: a fuse array including: fuse elements organized along a first direction and a second direction, wherein each fuse element is configured to store information, and a selection circuit configured to provide access to the fuse elements according to positions of the fuse elements along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse-read output based on reading from one or more of the fuse elements.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 31, 2019
    Inventors: John E. Riley, Girish N. Cherussery, Scott E. Smith, Yu-Feng Chen
  • Patent number: 10418073
    Abstract: Memory devices may have internal circuitry that employs voltages higher than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate, internally, higher voltages for operation. The available charge pumps in a memory device may be adjusted through adjustment of the operation frequency of oscillating circuitry that drives the charge pump. Delay elements may also be adjusted to facilitate operation of the charge pump.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harish N. Venkata, Yu-Feng Chen
  • Patent number: 10403330
    Abstract: Memory devices may have internal circuitry that employs voltages higher than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate, internally, higher voltages for operation. The number of available charge pumps in a memory device may be higher than the number used for certain memory operations. Gating circuitry may be used to selectively enable charge pump cores based on power demands that may be associated with a mode of operation and/or a command.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harish N. Venkata, Yu-Feng Chen
  • Publication number: 20190252209
    Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai
  • Publication number: 20190251321
    Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Chen-Hua Yu, Yu-Feng Chen, Chih-Hua Chen, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20190244004
    Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Yu-Chih Huang, Chih-Hua Chen, Yu-Jen Cheng, Chih-Wei Lin, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10373698
    Abstract: An electronic device including: a fuse array including fuse cells organized along a first direction and a second direction, wherein each fuse cell includes: a fuse element configured to store information, and a selection circuit configured to provide access to the fuse element according to a position of the fuse cell element along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse read output based on reading from one or more of the fuse cells simultaneously and in parallel.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: John E. Riley, Girish N. Cherussery, Scott E. Smith, Yu-Feng Chen
  • Patent number: 10366971
    Abstract: A structure includes a first package component, and a second package component over and bonded to the first package component. A supporting material is disposed in a gap between the first package component and the second package component. A molding material is disposed in the gap and encircling the supporting material.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chen Hsu, Yu-Feng Chen, Han-Ping Pu, Meng-Tse Chen, Guan-Yu Chen