Patents by Inventor Yu-feng Chen

Yu-feng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electronic device with a fuse-read trigger mechanism
    Patent number: 10360989
    Abstract: A method of operating an electronic device includes: generating a fuse read output based on reading a fuse cell at a predetermined data location in a fuse array, wherein the predetermined data location is configured to store predetermined data pattern; comparing the fuse read output to the predetermined data pattern; and generating a read-enable trigger based on the fuse read output matching the predetermined data pattern, wherein the read-enable trigger is for reading content stored in the fuse array and for broadcasting the content to circuits within the electronic device.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Raghukiran Sreeramaneni, John E. Riley, Yu-Feng Chen
  • Fingerprint sensor in InFO structure and formation method
    Patent number: 10354114
    Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Yu-Feng Chen, Chung-Shi Liu, Chen-Hua Yu, Hao-Yi Tsai, Yu-Chih Huang
  • SYSTEMS AND METHODS FOR IMPROVING FUSE SYSTEMS IN MEMORY DEVICES
    Publication number: 20190198127
    Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array comprising a plurality of fuses. The memory device additionally includes a first plurality of local fuse latches disposed outside of the fuse array and configured to provide redundancy for the plurality of memory addresses. The memory device also includes a fuse array broadcasting system comprising an N-bit bus system, wherein the N-bit bus system is communicatively coupled to the fuse array and to the first plurality of local fuse latches, and wherein the fuse array broadcasting system is configured to communicate fuse data from the fuse array to the first plurality of local fuse latches via the N-bit bus system.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: John E. Riley, Yu-Feng Chen, Scott E. Smith
  • Systems and methods for improving fuse systems in memory devices
    Patent number: 10332609
    Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array comprising a plurality of fuses. The memory device additionally includes a first plurality of local fuse latches disposed outside of the fuse array and configured to provide redundancy for the plurality of memory addresses. The memory device also includes a fuse array broadcasting system comprising an N-bit bus system, wherein the N-bit bus system is communicatively coupled to the fuse array and to the first plurality of local fuse latches, and wherein the fuse array broadcasting system is configured to communicate fuse data from the fuse array to the first plurality of local fuse latches via the N-bit bus system.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: John E. Riley, Yu-Feng Chen, Scott E. Smith
  • SYSTEMS AND METHODS FOR PLATE VOLTAGE REGULATION DURING MEMORY ARRAY ACCESS
    Publication number: 20190172518
    Abstract: A memory device may include a memory array comprising at least two sections. Each of the sections may further include multiple memory cells. The memory device may also include one or more controllers designed to receive one or more commands to initiate writing logical data to the multiple memory cells of a first section and a second section. Additionally, the writing may alternate between the first section and the second section until the first section and second section have been entirely written with the logical data.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 6, 2019
    Inventors: Yu-Feng Chen, Byung S. Moon, Myung Ho Bae, Harish N. Venkata
  • ELECTRONIC DEVICE WITH A FUSE-READ TRIGGER MECHANISM
    Publication number: 20190172546
    Abstract: A method of operating an electronic device includes: generating a fuse read output based on reading a fuse cell at a predetermined data location in a fuse array, wherein the predetermined data location is configured to store predetermined data pattern; comparing the fuse read output to the predetermined data pattern; and generating a read-enable trigger based on the fuse read output matching the predetermined data pattern, wherein the read-enable trigger is for reading content stored in the fuse array and for broadcasting the content to circuits within the electronic device.
    Type: Application
    Filed: December 4, 2017
    Publication date: June 6, 2019
    Inventors: Raghukiran Sreeramaneni, John E. Riley, Yu-Feng Chen
  • Semiconductor package and manufacturing process thereof
    Patent number: 10276402
    Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai
  • Fingerprint Sensor Pixel Array and Methods of Forming Same
    Publication number: 20190121952
    Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Fingerprint sensor device and method
    Patent number: 10268868
    Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yu-Feng Chen, Chih-Hua Chen, Hao-Yi Tsai, Chung-Shi Liu
  • Fingerprint sensor device and method
    Patent number: 10268872
    Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hua Chen, Yu-Jen Cheng, Chih-Wei Lin, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Contact area design for solder bonding
    Patent number: 10157874
    Abstract: A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Chun Tsai, Yu-Feng Chen, Tin-Hao Kuo, Chen-Shien Chen, Yu-Chih Huang, Sheng-Yu Wu
  • Fingerprint sensor pixel array and methods of forming same
    Patent number: 10157274
    Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Integrated circuit package and method of forming same
    Patent number: 10125014
    Abstract: Integrated circuit packages and methods of forming same are provided. A method includes attaching a first die and a second die to a carrier, the first die having a first contact pad, the second die having a second contact pad, the first contact pad and the second contact pad having different structures. A release layer is formed over the first die and the second die. An encapsulant is injected between the carrier and the release layer. One or more redistribution layers (RDLs) are formed over the first die, the second die and the encapsulant, the first contact pad and the second contact pad being in electrical contact with the one or more RDLs.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo Lung Pan, Chung-Shi Liu, Hao-Yi Tsai, Yu-Feng Chen, Yu-Jen Cheng
  • Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices
    Patent number: 10128208
    Abstract: In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hao-Cheng Hou, Yu-Feng Chen, Jung Wei Cheng, Yu-Min Liang, Tsung-Ding Wang
  • Package Substrates, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices
    Publication number: 20180204815
    Abstract: In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.
    Type: Application
    Filed: March 12, 2018
    Publication date: July 19, 2018
    Inventors: Hao-Cheng Hou, Yu-Feng Chen, Jung Wei Cheng, Yu-Min Liang, Tsung-Ding Wang
  • Protrusion bump pads for bond-on-trace processing
    Patent number: 10020276
    Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Shien Chen, Yu-Feng Chen, Yu-Wei Lin, Tin-Hao Kuo, Yu-Min Liang, Chun-Hung Lin
  • Fingerprint Sensor Pixel Array and Methods of Forming Same
    Publication number: 20180181738
    Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Fingerprint Sensor Device and Method
    Publication number: 20180173932
    Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.
    Type: Application
    Filed: February 19, 2018
    Publication date: June 21, 2018
    Inventors: Yu-Chih Huang, Chih-Hua Chen, Yu-Jen Cheng, Chih-Wei Lin, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Package Structures and Method of Forming the Same
    Publication number: 20180166364
    Abstract: Package structures and methods of forming package structures are described. A method includes placing a first package within a recess of a first substrate. The first package includes a first die. The method further includes attaching a first sensor to the first package and the first substrate. The first sensor is electrically coupled to the first package and the first substrate.
    Type: Application
    Filed: January 29, 2018
    Publication date: June 14, 2018
    Inventors: Chen-Hua Yu, Chih-Hua Chen, Hao-Yi Tsai, Yu-Feng Chen
  • Method of forming a semiconductor device including strain reduced structure
    Patent number: 9997480
    Abstract: A method of forming a device includes forming conductive pads on a semiconductor die. The conductive pads include a first conductive pad having a first width on a first region of the semiconductor die; and a second conductive pad having a second width on a second region of the semiconductor die. The method includes forming bonding pads on a substrate. The bonding pads include a third bonding pad having a third width on a third region of the substrate; and a fourth bonding pad having a fourth width on a fourth region of the substrate. The method further includes forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad. A ratio A of the first width to the third width is different from a ratio B of the second width to the fourth width.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Tsung-Yuan Yu, Yu-Feng Chen, Tsung-Ding Wang