Patents by Inventor Yu-Hao Ho

Yu-Hao Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10790365
    Abstract: An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 29, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin Lin, Yu-Hao Ho, Shin-Cheng Lin, Cheng-Tsung Wu
  • Patent number: 10695381
    Abstract: A tissue repair material derived from fish skin and manufacturing method thereof is applied to provide the tissue repair material suitable for use as a patch, a cover, a carrier, a scaffold, an implant or a reagent in various tissues. The tissue repair material has collagens to improve the wounded tissue repair, and has particular characters for desired tissue repair application. Furthermore, so far the factors of the terrestrial animal transmitted disease (caused by virus) do not survive on the tissue repair material derived from fish skin.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: June 30, 2020
    Assignee: BODY ORGAN BIOMEDICAL CORP.
    Inventors: Horng-Ji Lai, Min-Chang Huang, Jui-Min Ho, Yun-Ting Hsu, Yu-Chi Lin, Ta-Wei Su, Kuan-Hao Huang, Yu-Wei Chang
  • Patent number: 10692786
    Abstract: A semiconductor structure includes a substrate, a first insulating layer, a second insulating layer, a first seal ring structure, a second seal ring structure, and a passivation layer. The substrate has a chip region and a seal ring region. The first insulating layer is on the substrate. The second insulating layer is on the first insulating layer. The first seal ring structure is in the seal ring region and embedded in the first insulating layer and the second insulating layer, wherein the first seal ring structure includes a stack of metal layers. The second seal ring structure is in the seal ring region and embedded in the first insulating layer, wherein the second seal ring structure includes a polysilicon ring structure. The passivation layer is on the second insulating layer and the first seal ring structure.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 23, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-You Lin, Chi-Li Tu, Shin-Cheng Lin, Yu-Hao Ho, Cheng-Tsung Wu
  • Patent number: 10573738
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 25, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Patent number: 10475784
    Abstract: A semiconductor structure is provided. A substrate has a first conductivity type. A first well and a second well are formed in the substrate. The first well has a second conductivity type. The second well has the first conductivity type. A doped region is formed in the first well and has the second conductivity type. A gate structure is disposed over the substrate and overlaps a portion of the first well and a portion of the second well. An insulating layer is disposed over the substrate and is spaced apart from the gate structure. A conducting wire is disposed on the insulating layer and includes a first input terminal and a first output terminal. The first input terminal is configured to receive an input voltage. The first output terminal is electrically connected to the doped region.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: November 12, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Yu-Hao Ho, Shin-Cheng Lin, Wen-Hsin Lin, Cheng-Tsung Wu
  • Publication number: 20190267455
    Abstract: An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin LIN, Yu-Hao HO, Shin-Cheng LIN, Cheng-Tsung WU
  • Patent number: 10388649
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein the buried layer has a dopant concentration that is greater than that of the semiconductor substrate. The semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, and a first element disposed on the first region of the semiconductor substrate, wherein the first element includes a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) transistor. In addition, the semiconductor device includes a second element disposed on the second region of the semiconductor substrate, wherein the second element includes an ultra-high voltage (UHV) transistor.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 20, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chien-Wei Chiu, Shin-Cheng Lin, Yu-Hao Ho
  • Publication number: 20190157442
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Inventors: Shang-Hui TU, Chih-Jen HUANG, Jui-Chun CHANG, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
  • Patent number: 10262938
    Abstract: A semiconductor structure including a substrate, a first well, a first doped region, a second well, a second doped region, a field oxide, a first conductive layer, a first insulating layer and a second conductive layer is provided. Each of the substrate and the second well has a first conductivity type. The first and second wells are formed in the substrate. The first well has a second conductivity type. The first doped region is formed in the first well and has the second conductivity type. The second doped region is formed in the second well and has the first conductivity type. The field oxide is disposed on the substrate and is disposed between the first and second doped regions. The first conductive layer overlaps the field oxide. The first insulating layer overlaps the first conductive layer. The second conductive layer overlaps the first insulating layer.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 16, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Publication number: 20190103400
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein the buried layer has a dopant concentration that is greater than that of the semiconductor substrate. The semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, and a first element disposed on the first region of the semiconductor substrate, wherein the first element includes a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) transistor. In addition, the semiconductor device includes a second element disposed on the second region of the semiconductor substrate, wherein the second element includes an ultra-high voltage (UHV) transistor.
    Type: Application
    Filed: October 4, 2017
    Publication date: April 4, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chien-Wei CHIU, Shin-Cheng LIN, Yu-Hao HO
  • Publication number: 20190081042
    Abstract: A semiconductor device includes a substrate, first and second body regions, a well region, a source region, a drain region, and first and second doped regions. The first and second body regions are disposed in first and second regions respectively. The well region is disposed in the first and second regions and between the first and second body regions. First and second portions of the source region are disposed in the first and second body regions respectively. The drain region is disposed on the well region. The first doped region is disposed in the well region. The second doped region is disposed on the first doped region. A first portion of the first doped region and a first portion of the second doped region are disposed in the well region of the first region and extend toward the first body region and out of the well region.
    Type: Application
    Filed: September 8, 2017
    Publication date: March 14, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Tsung WU, Shin-Cheng LIN, Wen-Hsin LIN, Yu-Hao HO
  • Patent number: 10229907
    Abstract: A semiconductor device includes a substrate, first and second body regions, a well region, a source region, a drain region, and first and second doped regions. The first and second body regions are disposed in first and second regions respectively. The well region is disposed in the first and second regions and between the first and second body regions. First and second portions of the source region are disposed in the first and second body regions respectively. The drain region is disposed on the well region. The first doped region is disposed in the well region. The second doped region is disposed on the first doped region. A first portion of the first doped region and a first portion of the second doped region are disposed in the well region of the first region and extend toward the first body region and out of the well region.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: March 12, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho
  • Publication number: 20190067190
    Abstract: A semiconductor structure including a substrate, a first well, a first doped region, a second well, a second doped region, a field oxide, a first conductive layer, a first insulating layer and a second conductive layer is provided. Each of the substrate and the second well has a first conductivity type. The first and second wells are formed in the substrate. The first well has a second conductivity type. The first doped region is formed in the first well and has the second conductivity type. The second doped region is formed in the second well and has the first conductivity type. The field oxide is disposed on the substrate and is disposed between the first and second doped regions. The first conductive layer overlaps the field oxide. The first insulating layer overlaps the first conductive layer. The second conductive layer overlaps the first insulating layer.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Cheng-Tsung WU, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
  • Patent number: 10205014
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 12, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Patent number: 10181512
    Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: January 15, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hsin Lin, Shin-Cheng Lin, Cheng-Tsung Wu, Yu-Hao Ho
  • Publication number: 20190006355
    Abstract: A semiconductor structure is provided. A semiconductor substrate has a first conductivity type. A first well is formed in the semiconductor substrate and has a second conductivity type. A first well includes a first region and a second region. The dopant concentration of the first region is higher than the dopant concentration of the second region. A second well has the first conductivity type and is formed in the first region. A first doped region is formed in the first region and has the second conductivity type different than the first conductivity type. The second doped region has the first conductivity type and is formed in the second well. A third doped region has the first conductivity type and is formed in the second region. A fourth doped region has the second conductivity type and is formed in the first region.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin LIN, Shin-Cheng LIN, Cheng-Tsung WU, Yu-Hao HO
  • Patent number: 10170468
    Abstract: A semiconductor structure is provided. A semiconductor substrate has a first conductivity type. A first well is formed in the semiconductor substrate and has a second conductivity type. A first well includes a first region and a second region. The dopant concentration of the first region is higher than the dopant concentration of the second region. A second well has the first conductivity type and is formed in the first region. A first doped region is formed in the first region and has the second conductivity type different than the first conductivity type. The second doped region has the first conductivity type and is formed in the second well. A third doped region has the first conductivity type and is formed in the second region. A fourth doped region has the second conductivity type and is formed in the first region.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 1, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hsin Lin, Shin-Cheng Lin, Cheng-Tsung Wu, Yu-Hao Ho
  • Publication number: 20180350799
    Abstract: A semiconductor structure is provided. A substrate has a first conductivity type. A first well and a second well are formed in the substrate. The first well has a second conductivity type. The second well has the first conductivity type. A doped region is formed in the first well and has the second conductivity type. A gate structure is disposed over the substrate and overlaps a portion of the first well and a portion of the second well. An insulating layer is disposed over the substrate and is spaced apart from the gate structure. A conducting wire is disposed on the insulating layer and includes a first input terminal and a first output terminal. The first input terminal is configured to receive an input voltage. The first output terminal is electrically connected to the doped region.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 6, 2018
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yu-Hao HO, Shin-Cheng LIN, Wen-Hsin LIN, Cheng-Tsung WU
  • Patent number: 10128331
    Abstract: A high-voltage semiconductor device is provided. The device includes an epitaxial layer formed on a semiconductor substrate. The semiconductor substrate includes a first doping region having a first conductivity type. The epitaxial layer includes a body region that has a second conductivity type and a second doping region and a third doping region that have the first conductivity type. The second doping region and the third doping region are respectively on both opposite sides of the body region. A source region and a drain region are respectively in the body region and the second doping region. A gate structure is on the epitaxial layer. A fourth doping region having the second conductivity region is below the source region and adjacent to the bottom of the body region. The fourth doping region has a doping concentration greater than that of the body region.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: November 13, 2018
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Tsung Wu, Shin-Cheng Lin, Wen-Hsin Lin, Yu-Hao Ho
  • Publication number: 20180308934
    Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.
    Type: Application
    Filed: January 10, 2018
    Publication date: October 25, 2018
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin LIN, Shin-Cheng LIN, Cheng-Tsung WU, Yu-Hao HO