Patents by Inventor Yu-Hao Hsu
Yu-Hao Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12380945Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.Type: GrantFiled: January 19, 2024Date of Patent: August 5, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
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Patent number: 12346143Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.Type: GrantFiled: April 22, 2024Date of Patent: July 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
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Publication number: 20250140311Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.Type: ApplicationFiled: January 6, 2025Publication date: May 1, 2025Inventors: Jui-Che Tsai, Chen-Lin Yang, Yu-Hao Hsu, Shih-Lien Linus Lu
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Publication number: 20250104753Abstract: A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.Type: ApplicationFiled: December 10, 2024Publication date: March 27, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsien HUANG, Wei-Jer HSIEH, Yu-Hao HSU
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Patent number: 12211587Abstract: A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.Type: GrantFiled: June 16, 2023Date of Patent: January 28, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsien Huang, Wei-Jer Hsieh, Yu-Hao Hsu
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Patent number: 12190945Abstract: A memory device includes a memory cell array including a plurality of bit cells, each of the bit cells coupled to one of a plurality of bit lines and one of a plurality of word lines, respectively, wherein each of the plurality of bit cells is configured to: present an initial logic state during a random number generator (RNG) phase; and operate as a memory cell at a first voltage level during a SRAM phase; and a controller controlling bit line signals on the plurality of bit lines and word line signals on the plurality of word lines, wherein the controller is configured to: during the RNG phase, precharge the plurality of bit lines to a second voltage level, and determine the initial logic states of the plurality of bit cells to generate at least one random number, wherein the second voltage level is lower than the first voltage level.Type: GrantFiled: April 10, 2023Date of Patent: January 7, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Che Tsai, Chen-Lin Yang, Yu-Hao Hsu, Shih-Lien Linus Lu
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Publication number: 20250006256Abstract: A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a word line driver connected to a word line, a row of memory cells connected to the word line, each memory cell powered by a first supply voltage, and a power circuit. The power circuit is configured to provide the first supply voltage to the word line driver when a read condition is satisfied, and a second supply voltage to the word line driver when the read condition is not satisfied, the second supply voltage being less than the first supply voltage.Type: ApplicationFiled: September 16, 2024Publication date: January 2, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Hsien Huang, Wei-Jer Hsieh, Tsung-Yuan Huang, Yu-Hao Hsu
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Publication number: 20240395333Abstract: A memory circuit includes first and second write lines and memory segments. A first driver includes, between power and reference nodes, a PMOS transistor and a first inverter including an input coupled to a first driver first input and an output coupled to the first write line, and a second inverter coupled between the PMOS transistor gate and a first driver second input. A second driver includes, between the power and reference nodes, a PMOS transistor and a third inverter including an input coupled to a second driver first input and an output coupled to the second write line, and a fourth inverter coupled between the PMOS transistor gate and a second driver second input. Each of the first driver first input and second driver second input receives a first data signal, and each of the first driver second input and second driver first input receives a second data signal.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Inventors: Manish ARORA, Yen-Huei CHEN, Hung-Jen LIAO, Nikhil PURI, Yu-Hao HSU
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Patent number: 12136460Abstract: A memory circuit includes first and second memory segments coupled to first and second write lines, and first and second write line circuits coupled to the first and second write lines and configured to receive first and second data signals. The first and second data signals have complementary low and high logical states during a write operation to the first or second memory segment, and each of the first and second data signals has the low logical state during a masked write operation to the first or second memory segment. The first and second write line circuits output, to the first and second write lines, first and second write line signals responsive to the first and second data signals during the write operation and float the first and second data lines during the masked write operation.Type: GrantFiled: July 31, 2023Date of Patent: November 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Manish Arora, Yen-Huei Chen, Hung-Jen Liao, Nikhil Puri, Yu-Hao Hsu
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Publication number: 20240361819Abstract: A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal according to a first power supply signal from a first power supply and a status signal. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal, according to the first power management signal and the status signal.Type: ApplicationFiled: July 5, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chen KUO, Yangsyu LIN, Yu-Hao HSU, Cheng Hung LEE, Hung-Jen LIAO
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Patent number: 12125525Abstract: A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a word line driver connected to a word line, a row of memory cells connected to the word line, each memory cell powered by a first supply voltage, and a power circuit. The power circuit is configured to provide the first supply voltage to the word line driver when a read condition is satisfied, and a second supply voltage to the word line driver when the read condition is not satisfied, the second supply voltage being less than the first supply voltage.Type: GrantFiled: February 11, 2022Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsien Huang, Wei-jer Hsieh, Tsung-Yuan Huang, Yu-Hao Hsu
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Patent number: 12072750Abstract: A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal according to a first power supply signal from a first power supply and a status signal. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal, according to the first power management signal and the status signal.Type: GrantFiled: June 20, 2023Date of Patent: August 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chen Kuo, Yangsyu Lin, Yu-Hao Hsu, Cheng Hung Lee, Hung-Jen Liao
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Publication number: 20240272666Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.Type: ApplicationFiled: April 22, 2024Publication date: August 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
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Patent number: 11989046Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.Type: GrantFiled: February 6, 2023Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
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Publication number: 20240161822Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.Type: ApplicationFiled: January 19, 2024Publication date: May 16, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
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Patent number: 11915746Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.Type: GrantFiled: May 12, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
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Patent number: D1028858Type: GrantFiled: October 5, 2021Date of Patent: May 28, 2024Assignee: Cheng Shin Rubber Industrial Co., Ltd.Inventors: Min-Chi Lin, Yi-Ta Lu, Yi-Zhen Huang, Ssu Yu Kuo, Yu-Hao Hsu, Jyun De Li, Yu Nan Sung, Jyun-Yi Ke
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Patent number: D1054364Type: GrantFiled: October 5, 2021Date of Patent: December 17, 2024Assignee: Cheng Shin Rubber Industrial Co., Ltd.Inventors: Min-Chi Lin, Yi-Ta Lu, Yi-Zhen Huang, Yu-Shiang Lai, Yu-Chia Hsieh, Jyun De Li, Yu-Hao Hsu, Jyun-Yi Ke
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Patent number: D1070730Type: GrantFiled: January 17, 2023Date of Patent: April 15, 2025Assignee: Cheng Shin Rubber Ind. Co., Ltd.Inventors: Min-Chi Lin, Yu-Hao Hsu, Chen-Yang Yu, Jyun-Yi Ke, Cheng-Yu Li, Yi-Zhen Huang
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Patent number: D1078595Type: GrantFiled: August 21, 2023Date of Patent: June 10, 2025Inventors: Min Chi Lin, Yu Hao Hsu, Chen Yang Yu, Jyun Yi Ke, Yu Chia Hsieh