Patents by Inventor Yu-Hao Hsu
Yu-Hao Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200020363Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Publication number: 20200005835Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.Type: ApplicationFiled: January 31, 2019Publication date: January 2, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Chi WU, Cheng Hung LEE, Chien-Kuo SU, Chiting CHENG, Yu-Hao HSU, Yangsyu LIN
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Publication number: 20200005877Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, a first input node configured to receive a first data signal, a second input node configured to receive a second data signal, a third input node configured to receive a control signal, and an output node. The write line circuit is configured to, responsive to the first data signal, the second data signal, and the control signal, either output one of the power supply voltage level or the reference voltage level on the output node, or float the output node.Type: ApplicationFiled: November 29, 2018Publication date: January 2, 2020Inventors: Manish ARORA, Hung-Jen LIAO, Yen-Huei CHEN, Nikhil PURI, Yu-Hao HSU
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Patent number: 10510380Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.Type: GrantFiled: April 23, 2019Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Patent number: 10503421Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.Type: GrantFiled: March 28, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Hsu, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
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Publication number: 20190252008Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.Type: ApplicationFiled: April 23, 2019Publication date: August 15, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Patent number: 10304500Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.Type: GrantFiled: February 22, 2018Date of Patent: May 28, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Publication number: 20190005990Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.Type: ApplicationFiled: February 22, 2018Publication date: January 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Fu-An Wu, Cheng Hung Lee, Chen-Lin Yang, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Publication number: 20190004718Abstract: Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption.Type: ApplicationFiled: March 28, 2018Publication date: January 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Yu-Hao HSU, Cheng Hung Lee, Chen-Lin Yang, Chiting Cheng, Fu-An Wu, Hung-Jen Liao, Jung-Ping Yang, Jonathan Tsung-Yung Chang, Wei Min Chan, Yen-Huei Chen, Yangsyu Lin, Chien-Chen Lin
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Patent number: 9898983Abstract: A source driving device for a display system includes a receiving module, for receiving display data; a register module, for sorting pixel data included in the display data to generate sorted pixel data; a latch module, for outputting sequenced display data to the level shifting module; a level shifting module, for adjusting the sequenced display data from a low voltage range to a medium voltage range; a converting module; for converting the sequenced display data to analog display voltages; a buffer module, for generating a plurality source driving signals according to the analog display voltages; and an output switching module, for outputting the plurality source driving signals to a display device of the display system operating in a high voltage range; wherein circuit components in the source driving device operating in different voltage ranges have different gate oxide thicknesses.Type: GrantFiled: November 6, 2016Date of Patent: February 20, 2018Assignee: NOVATEK Mircroelectronics Corp.Inventors: Yu-Hao Hsu, Jui-Chang Lin, Ming-Han Lee, Wei-Cheng Lin
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Publication number: 20180047355Abstract: A source driving device for a display system includes a receiving module, for receiving display data; a register module, for sorting pixel data included in the display data to generate sorted pixel data; a latch module, for outputting sequenced display data to the level shifting module; a level shifting module, for adjusting the sequenced display data from a low voltage range to a medium voltage range; a converting module; for converting the sequenced display data to analog display voltages; a buffer module, for generating a plurality source driving signals according to the analog display voltages; and an output switching module, for outputting the plurality source driving signals to a display device of the display system operating in a high voltage range; wherein circuit components in the source driving device operating in different voltage ranges have different gate oxide thicknesses.Type: ApplicationFiled: November 6, 2016Publication date: February 15, 2018Inventors: Yu-Hao Hsu, Jui-Chang Lin, Ming-Han Lee, Wei-Cheng Lin
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Patent number: 9685224Abstract: A memory comprises a first set of memory cells coupled between a first data line and a second data line. The memory also includes a first input/output (I/O) circuit coupled to the first data line and the second data line. The first I/O circuit is also coupled to a first control line to receive a first control signal and coupled to a first select line to receive a first select signal. The first I/O circuit is configured to selectively decouple the first data line and the second data line from the first I/O circuit during a sleep mode based on the first control signal and the first select signal.Type: GrantFiled: May 15, 2015Date of Patent: June 20, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Lin Yang, Cheng Hung Lee, Hung-Jen Liao, Kao-Cheng Lin, Jonathan Tsung-Yung Chang, Yu-Hao Hsu
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Patent number: 9659603Abstract: A power management circuit for an electronic device sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.Type: GrantFiled: December 28, 2015Date of Patent: May 23, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hektor Huang, Yangsyu Lin, Yu-Hao Hsu, Chia-En Huang, Chiting Cheng, Chen-Lin Yang, Jung-Ping Yang, Cheng Hung Lee
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Publication number: 20170040042Abstract: A power management circuit for an electronic device is disclosed that sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits.Type: ApplicationFiled: December 28, 2015Publication date: February 9, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hektor Huang, Yangsyu Lin, Yu-Hao Hsu, Chia-En Huang, Chiting Cheng, Chen-Lin Yang, Jung-Ping Yang, Cheng Hung Lee
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Patent number: 9389786Abstract: A memory device includes storage layers each comprising memory cells arranged in a plurality of rows, bit lines coupled to the memory cells in the corresponding rows, tracking cells arranged in at least one row, at least one tracking bit line coupled to the tracking cells, and at least one sense amplifier coupled to the bit lines. The sense amplifier is configured to detect data stored in the memory cells, and has an enabling terminal coupled to the at least one tracking bit line. The memory device further comprises word lines and tracking word lines extending through the storage layers. The word lines are coupled to the corresponding memory cells in the storage layers. The tracking word lines are coupled to the corresponding tracking cells in the storage layers.Type: GrantFiled: June 10, 2014Date of Patent: July 12, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Chien Tsai, Yu-Hao Hsu, Chih-Yu Lin, Chen-Lin Yang, Cheng Hung Lee
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Patent number: 9390816Abstract: An integrated circuit has a first circuit portion on a first level and a second circuit portion on a second level different from the first level. The first circuit portion includes a first cell having a first voltage value at a first node and a second voltage value at a second node. The second circuit portion includes a second cell coupled with the first cell, the second cell being selectively controllable to supply a voltage to the first cell based on an instruction to supply the voltage. The instruction to supply the voltage is based on a determined mismatch between the first voltage value and the second voltage value being greater than a predetermined threshold value.Type: GrantFiled: December 28, 2015Date of Patent: July 12, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Hsu, Chia-En Huang, Hektor Huang, Yi-Ching Chang, Chen-Lin Yang, Jung-Ping Yang, Cheng Hung Lee
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Patent number: 9368570Abstract: An integrated circuit for a driving device is disclosed. The integrate circuit includes a substrate comprising a high-voltage area and a low-voltage area; a plurality of first trenches, formed in the high-voltage area; a plurality of first isolations, formed in the plurality of first trenches of the high-voltage area; a plurality of second trenches, formed in the low-voltage area; and a plurality of second isolations, formed in the plurality of second trenches of the low-voltage area; wherein a depth difference exists between each of the plurality of first trenches and each of the plurality of second trenches.Type: GrantFiled: September 24, 2014Date of Patent: June 14, 2016Assignee: NOVATEK Microelectronics Corp.Inventors: Yu-Hao Hsu, Jui-Chang Lin
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Publication number: 20160133342Abstract: An integrated circuit has a first circuit portion on a first level and a second circuit portion on a second level different from the first level. The first circuit portion includes a first cell having a first voltage value at a first node and a second voltage value at a second node. The second circuit portion includes a second cell coupled with the first cell, the second cell being selectively controllable to supply a voltage to the first cell based on an instruction to supply the voltage. The instruction to supply the voltage is based on a determined mismatch between the first voltage value and the second voltage value being greater than a predetermined threshold value.Type: ApplicationFiled: December 28, 2015Publication date: May 12, 2016Inventors: Yu-Hao HSU, Chia-En HUANG, Hektor HUANG, Yi-Ching CHANG, Chen-Lin YANG, Jung-Ping YANG, Cheng Hung LEE
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Publication number: 20160111142Abstract: A memory comprises a first set of memory cells coupled between a first data line and a second data line. The memory also includes a first input/output (I/O) circuit coupled to the first data line and the second data line. The first I/O circuit is also coupled to a first control line to receive a first control signal and coupled to a first select line to receive a first select signal. The first I/O circuit is configured to selectively decouple the first data line and the second data line from the first I/O circuit during a sleep mode based on the first control signal and the first select signal.Type: ApplicationFiled: May 15, 2015Publication date: April 21, 2016Inventors: Chen-Lin YANG, Cheng Hung LEE, Hung-Jen LIAO, Kao-Cheng LIN, Jonathan Tsung-Yung CHANG, Yu-Hao HSU
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Patent number: 9240233Abstract: An integrated circuit comprises a first circuit portion comprising a plurality of first cells, each first cell comprising a first transistor having a first voltage value at a first node, and a second transistor having a second voltage value at a second node. A second circuit portion comprises a plurality of second cells. The second cells are individually coupled with a corresponding first cell of the plurality of first cells. The second cells are selectively controllable to supply a voltage to one or more of the first cells based on an instruction to supply the voltage. The instruction to supply the voltage is based on a determined mismatch between the first voltage value and the second voltage value being greater than a predetermined threshold value.Type: GrantFiled: November 12, 2014Date of Patent: January 19, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Hao Hsu, Chia-En Huang, Hektor Huang, Yi-Ching Chang, Chen-Lin Yang, Jung-Ping Yang, Cheng Hung Lee