Abstract: An integrated circuit for a driving device is disclosed. The integrate circuit includes a substrate comprising a high-voltage area and a low-voltage area; a plurality of first trenches, formed in the high-voltage area; a plurality of first isolations, formed in the plurality of first trenches of the high-voltage area; a plurality of second trenches, formed in the low-voltage area; and a plurality of second isolations, formed in the plurality of second trenches of the low-voltage area; wherein a depth difference exists between each of the plurality of first trenches and each of the plurality of second trenches.

Abstract: A memory device includes storage layers each comprising memory cells arranged in a plurality of rows, bit lines coupled to the memory cells in the corresponding rows, tracking cells arranged in at least one row, at least one tracking bit line coupled to the tracking cells, and at least one sense amplifier coupled to the bit lines. The sense amplifier is configured to detect data stored in the memory cells, and has an enabling terminal coupled to the at least one tracking bit line. The memory device further comprises word lines and tracking word lines extending through the storage layers. The word lines are coupled to the corresponding memory cells in the storage layers. The tracking word lines are coupled to the corresponding tracking cells in the storage layers.

Abstract: A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal.

Abstract: A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.

Abstract: A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.

Abstract: An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals.

Abstract: An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals.

Abstract: A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal.

Abstract: A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.

Abstract: A wordline tracking circuit and corresponding method are disclosed, and include a tracking wordline having an impedance characteristic associated therewith that models a row of memory cells in a memory device, wherein the tracking wordline row has a near end that receives a wordline pulse signal having a near end rising pulse edge and a near end falling pulse edge. The tracking wordline also has a far end. A tracking cell component is coupled to the far end of the tracking wordline that receives the wordline pulse signal. Lastly, the circuit includes a tracking bitline pre-charge circuit coupled to the tracking cell that is configured to pre-charge a tracking bitline associated with the tracking cell using the near end wordline pulse signal.

Abstract: A defected ground structure with shielding effect is provided. The structure includes a dielectric layer, a defected metal layer, a grounded metal layer and at least a conductive mushroom-like structure. The defected metal layer has a line-shaped opening and is disposed in the dielectric layer. The conductive mushroom-like structure is disposed between the defected metal layer and the grounded metal layer and is arranged along an extending direction of the line-shaped opening periodically. The conductive mushroom-like structure includes a laterally extending member and a vertically extending member. The laterally extending member is parallel to the defected metal layer and a distance is maintained away from the defected metal layer. The projection area of the laterally extending member on the defected metal layer covers a length of the line-shaped opening corresponding to the laterally extending member. The vertically extending member connects the laterally extending member and the grounded metal layer.

Abstract: A defected ground structure with shielding effect is provided. The structure includes a dielectric layer, a defected metal layer, a grounded metal layer and at least a conductive mushroom-like structure. The defected metal layer has a line-shaped opening and is disposed in the dielectric layer. The conductive mushroom-like structure is disposed between the defected metal layer and the grounded metal layer and is arranged along an extending direction of the line-shaped opening periodically. The conductive mushroom-like structure includes a fungating part and a stipe part. The fungating part is parallel to the defected metal layer and a distance is maintained away from the defected metal layer. The projection area of the fungating part on the defected metal layer covers a length of the line-shaped opening corresponding to the fungating part. The stipe part connects the fungating part and the grounded metal layer.

Abstract: A broadband high output current output stage includes at least one first differential pair for enhancing the bandwidth. A second differential pair is further disposed in the circuit. The second differential pair is coupled to one of the first differential pair, such that a large output voltage swing is distributed to all transistors to avoid breakdowns thereof. A feedback unit is connected between each bias unit and the first differential pair. The first compensation unit compensates the electric characteristic of the high-frequency zero of the feedback unit and the bias unit, thereby broadening the linear bandwidth of the frequency response. The second compensation units are disposed between the first differential pairs. Each second compensation unit compensates the high-frequency zero of the node where each two first differential pairs are cascaded, thereby further broadening the linear bandwidth of the frequency response.

Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plug is disposed in the dielectric layer electrically connecting with the conductive part, and includes a first plug and a second plug on the first plug, wherein the material or the critical dimension of the second plug is different from that of the first plug. The conductive line is disposed on the dielectric layer electrically connecting with the composite plug.

Abstract: The invention discloses an active back-end termination circuit, which comprises a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor and the first transistor are connected in series for forming a first impendence unit. A first source of the first transistor is connected to a working voltage with VTT. The second resistor and the second transistor are connected in series for forming a second impendence unit. A second gate and a second drain of the second transistor are connected to the working voltage with VTT. Wherein, the first impendence unit and the second impendence unit are connected in parallel. The first transistor or the second transistor is switched on through a power source, and the first transistor and the second transistor change the impedance actively for matching a load according to the voltage source.

Abstract: The invention discloses an active back-end termination circuit, which comprises a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor and the first transistor are connected in series for forming a first impendence unit. A first source of the first transistor is connected to a working voltage with VTT. The second resistor and the second transistor are connected in series for forming a second impendence unit. A second gate and a second drain of the second transistor are connected to the working voltage with VTT. Wherein, the first impendence unit and the second impendence unit are connected in parallel. The first transistor or the second transistor is switched on through a power source, and the first transistor and the second transistor change the impedance actively for matching a load according to the voltage source.

Abstract: A broadband high output current output stage includes at least one first differential pair for enhancing the bandwidth. A second differential pair is further disposed in the circuit. The second differential pair is coupled to one of the first differential pair, such that a large output voltage swing is distributed to all transistors to avoid breakdowns thereof. A feedback unit is connected between each bias unit and the first differential pair. The first compensation unit compensates the electric characteristic of the high-frequency zero of the feedback unit and the bias unit, thereby broadening the linear bandwidth of the frequency response. The second compensation units are disposed between the first differential pairs. Each second compensation unit compensates the high-frequency zero of the node where each two first differential pairs are cascaded, thereby further broadening the linear bandwidth of the frequency response.

Abstract: A system-on-chip (SoC) that is immune to electromagnetic interference has block shield rings fabricated therein. The SoC includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated circuit from electromagnetic interference. The EMI shield ring is grounded and includes a metal rampart consisting of multi-layer metals and vias. A pickup diffusion is connected to the metal rampart. In one embodiment, the memory block is also shielded.

Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plug is disposed in the dielectric layer electrically connecting with the conductive part, and includes a first plug and a second plug on the first plug, wherein the material or the critical dimension of the second plug is different from that of the first plug. The conductive line is disposed on the dielectric layer electrically connecting with the composite plug.

Abstract: A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed on an insulation structure, at least a contact formed on the insulation structure aside, and a metal layer formed on the contact. Another embodiment of the second test key may comprise at least a gate formed on the semiconductor substrate, a contact formed aside, and a metal layer formed on the contact. Further another embodiment uses a test key comprising at least an elongated gate and an elongated doping region aside, and only one or a few contacts are formed on an end portion of the elongated doping region.