Abstract: A method to extract gate to source/drain and overlap capacitances is disclosed. A first capacitance of a first test key having a reference structure and a second capacitance of a second test key having a novel structure are measured. The second test key may comprise at least a gate formed on an insulation structure, at least a contact formed on the insulation structure aside, and a metal layer formed on the contact. Another embodiment of the second test key may comprise at least a gate formed on the semiconductor substrate, a contact formed aside, and a metal layer formed on the contact. Further another embodiment uses a test key comprising at least an elongated gate and an elongated doping region aside, and only one or a few contacts are formed on an end portion of the elongated doping region.

Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plug is disposed in the dielectric layer electrically connecting with the conductive part, and includes a first plug and a second plug on the first plug, wherein the material or the critical dimension of the second plug is different from that of the first plug. The conductive line is disposed on the dielectric layer electrically connecting with the composite plug.

Abstract: An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is disposed on the substrate covering the conductive part. The composite plug is disposed in the dielectric layer electrically connecting with the conductive part, and includes a first plug and a second plug on the first plug, wherein the material or the critical dimension of the second plug is different from that of the first plug. The conductive line is disposed on the dielectric layer electrically connecting with the composite plug.

Abstract: A system-on-chip (SoC) that is immune to electromagnetic interference has block shield rings fabricated therein. The SoC includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated circuit from electromagnetic interference. The EMI shield ring is grounded and includes a metal rampart consisting of multi-layer metals and vias. A pickup diffusion is connected to the metal rampart. In one embodiment, the memory block is also shielded.

Abstract: A system-on-chip (SoC) that is immune to electromagnetic interference has block shield rings fabricated therein. The SoC includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated circuit from electromagnetic interference. The EMI shield ring is grounded and includes a metal rampart consisting of multi-layer metals and vias. A pickup diffusion is connected to the metal rampart. In one embodiment, the memory block is also shielded.

Abstract: A system-on-chip (SoC) that is immune to electromagnetic interference has block shield rings fabricated therein. The SoC includes a microprocessor core; an on-chip bus interface; an embedded memory block; and an analog/mixed-signal integrated circuit shielded by an EMI shield ring encircling the analog/mixed-signal integrated circuit for protecting the analog/mixed-signal integrated circuit from electromagnetic interference. The EMI shield ring is grounded and includes a metal rampart consisting of multi-layer metals and vias. A pickup diffusion is connected to the metal rampart. In one embodiment, the memory block is also shielded.

Abstract: An interconnection layout is provided. The interconnection layout includes a lower metal wiring layer (Metal—n) being drawn in a first direction; an upper metal wiring layer (Metal—n+1) being drawn in a 45-degree direction with respect to a second direction being normal to the first direction; and a first and second metal vias having different dimensions interposed between the lower metal wiring layer and the upper metal wiring layer for electrically connected the two metal wiring layers, and wherein the first metal via has the dimension that is larger than the dimension of the second metal via thereby compensating non-uniform current flowing through one of the two metal wiring layers.

Abstract: A control method and apparatus used for a bias controller of automatic bias correction on an optical modulator of optical emitter of external modulation type is a close-loop control system, composed of a base signal generator, an optical receiver, a second-order harmonic signal generator, a second-order harmonic signal detector, a DC amplifier, and a temperature automatic correction device. The bias voltage point of the optical modulator can remain a constant, whereby the optical power can be exported in stable level and distortion of transmission is reduced. It can be avoided about the effect of the environmental temperature, resulting in the change of optical output and the additional signal distortion of the transmission signal.