Abstract: A physiological detection method includes the following steps. A detection portion of a human body is detected to obtain a detection signal. Then, the detection signal is processed to output a digital physiological signal. The digital physiological signal is received to calculate and obtain first information and second information related to feature points thereof. Then, a ratio of the second information to the first information is calculated to obtain a physiological condition index. The digital physiological signal includes pulse waves generated according to a time sequence. The feature points of the digital physiological signal include a wave pulse peak and a foot point located at a forepart of the rising edge of the wave. In addition, a physiological detection device is also introduced.

Abstract: A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved.

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: reading data from a plurality of first memory cells of a rewritable non-volatile memory module; estimating an error bit occurrence rate of the data before performing a first decoding process on the data; and performing the first decoding process on the data by using a first decoding parameter according to the estimated error bit occurrence rate, wherein the first decoding parameter corresponds to a strict level for locating an error bit in the first decoding process. As a result, a decoding efficiency of the memory storage device can be improved.

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Abstract: An industrial robot includes an actuator and a driver. The actuator serves to provide power inside so as to create a predetermined motional form. The driver serves to drive an internal power source of the actuator to output power. The driver is adjacently and fixedly connected with one end of the actuator. A power unit is disposed in the actuator for generating power. The power unit has an output shaft. The actuator has a transmission unit for transmitting the power to make an operation unit move in the predetermined motional form. The transmission unit has a transmission shaft. The output shaft and the transmission shaft are coaxially and integrally formed.

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

Abstract: A software defined networking (SDN) system and network connection routing method thereof are provided. The SDN system includes an SDN controlling server and an SDN switch. The SDN switch receives client network packets from a client device and transmits the client network packets to the SDN controlling server. The SDN controlling server determines a connection route of the client device according to the client network packets and server loading information. The SDN controlling server transmits the connection route to the SDN switch. The SDN switch stores the connection route and transmits the client network packets to one of servers based on the connection route.

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit; performing a parity check procedure for the hard bit to obtain a plurality of syndromes; determining whether the hard bit has error according to the syndromes; if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit.

Abstract: A hydrogen generating device includes a first housing, a porous structure, a first flow-guiding structure and a heating unit. The first housing accommodates a solid reactant. The porous structure is disposed in the first housing. The first flow-guiding structure has first and second end portions opposite to each other. The first end portion is connected to the porous structure. The second end portion protrudes outside the first housing and is connected to the heating unit. A liquid reactant passing through the second end portion is gasified into a gaseous reactant through the heating unit. The gaseous reactant passing through the first end portion reaches to the porous structure and then is diffused from the porous structure into the first housing, so that the gaseous reactant and the solid reactant react and generate a hydrogen gas. A power generating equipment including the hydrogen generating device is also provided.

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract: A hydrogen purification device including a container, a first opening structure and a second opening structure is provided. The container has at least a filter material inside. The first opening structure is disposed in the container, wherein hydrogen-rich gas mixture flows into the container via the first opening structure so that purified hydrogen gas is generated by conducting a reaction between the hydrogen-rich gas mixture and the filter material. Besides, a second opening structure is disposed in the container, wherein the purified hydrogen gas flows away from the container via the second opening structure. A fuel processor having the hydrogen purification device is also provided.

Abstract: A method for manufacturing a semiconductor device having a metal gate includes forming a filling layer and a high-K gate dielectric layer in the first recess between a pair of spacers, wherein the high-K gate dielectric layer and the filling layer are stacked in the first recess sequentially, and an exposed top surface of the high-K gate dielectric layer and a top surface of the filling layer are lower than a top surface of each spacer; and removing a part of each spacer and widening the first recess on the top surface of the filling layer to form a second recess, wherein a width of the second recess is larger than a width of the first recess.

Abstract: The communication system comprises a base station (BS), a femtocell and a core network. The femtocell deployed within the signal coverage of the BS establishes a first wired connection with an internet service provider (ISP) network and a first wireless connection with a user equipment (UE). The core network establishes a second wired connection with the ISP network and a third wired connection with the BS. The core network is configured to determine that a voice data transmission service is about to be provided to the UE, and transmit a first radio access bearer (RAB) setup request message to the BS to enable the BS to establish a second wireless connection with the femtocell according to the first RAB setup request message so that the UE performs a voice data transmission with the core network via the first wireless connection, the second wireless connection and the third wired connection.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.

Abstract: An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably.

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading at least one memory cell according to a first read voltage to obtain at least one first verification bit; executing a hard bit mode decoding procedure according to the first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure; if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the memory cell; deciding a voltage number according to the storage information; reading the memory cell according to second read voltages matching the voltage number to obtain second verification bits; and executing a soft bit mode decoding procedure according to the second verification bits. Accordingly, the speed of decoding is increased.

Abstract: The present invention provides a light-emitting module, which comprises a light-emitting device, a light-guiding member, and an external light-guiding member. The light-emitting device emits light. The light-guiding member is disposed on the light-emitting path of the light-emitting module; the external light-guiding member is disposed on the light-emitting path of the light-emitting member. The light-guiding member distributes the light over the light-incidence surface of the external light-guiding member uniformly. After the external light-guiding member, the light is modified to axially symmetric light. Besides, the light-emitting device is disposed in a reflection ring, and a diffuser is disposed on the light-emitting path of the light-emitting device. When a minority of the light-emitting device fail, although the overall energy of the light source is reduced, the influence on the light emission of the light-emitting module is not significant.

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved.