Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a first fin structure and a second fin structure over a substrate. The method also includes partially removing the substrate to form a trench between the first fin structure and the second fin structure and forming a sacrificial structure to fill the trench. The method further includes forming an epitaxial structure on the first fin structure and forming a conductive contact over the epitaxial structure and the sacrificial structure. In addition, the method includes replacing the sacrificial structure with a conductive structure.

Abstract: An optical structure and methods of forming an optical structure are provided. In some embodiments, the optical structure includes a substrate having a frontside and a backside opposite the frontside, a plurality of image-sensing elements arranged within the substrate, and a deep trench isolation (DTI) structure disposed between adjacent image-sensing elements. The DTI structure extends from the backside of the substrate to a first depth within the substrate and laterally surrounds the plurality of image-sensing elements. The optical structure further includes a light transmission layer formed over the backside of the substrate. The light transmission layer includes a first side and a second side adjacent to the backside of the substrate. The optical structure further includes a buried grid structure in the light transmission layer, the buried grid structure extending from the first side of the light transmission layer to a second depth within the light transmission layer.

Abstract: A device includes a substrate, gate stacks, source/drain (S/D) features over the substrate, S/D contacts over the S/D features, and one or more dielectric layers over the gate stacks and the S/D contacts. A via structure penetrates the one or more dielectric layers and electrically contacts one of the gate stacks and the S/D contacts. And a ferroelectric (FE) stack is over the via structure and directly contacting the via structure, wherein the FE stack includes an FE feature and a top electrode over the FE feature.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a channel member having a longitudinal axis in a first direction, and the channel member has a first portion and a second portion separated from each other by a blank region. The semiconductor structure also includes a first gate structure formed over the blank region and having a longitudinal axis in a second direction different from the first direction and an isolation structure formed in the blank region and abutting the first gate structure in the second direction. The semiconductor structure also includes a through via structure formed through the isolation structure. In addition, the through via structure includes a first conductive filling layer, and a first air gap is sandwiched between the first conductive filling layer and the isolation structure.

Abstract: A touch sensing method for a touch panel includes following operations: entering a first touch sensing process and performing a non-water mode; determining whether there is water on the touch panel in the first touch sensing process; entering a second touch sensing process and performing a water mode when there is water detected on the touch panel in the first touch sensing process; determining whether there is water on the touch panel in the second touch sensing process; and entering the first touch sensing process and performing the non-water mode when there is no water detected on the touch panel in the second touch sensing process.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined by a low-transmission layer. In some embodiments, the image sensor comprises an array of pixels and the inter-pixel trench isolation structure. The array of pixels is on a substrate, and the pixels of the array comprise individual photodetectors in the substrate. The inter-pixel trench isolation structure is in the substrate. Further, the inter-pixel trench isolation structure extends along boundaries of the pixels, and individually surrounds the photodetectors, to separate the photodetectors from each other. The inter-pixel trench isolation structure is defined by a low-transmission layer with low transmission for incident radiation, such that the inter-pixel trench isolation structure has low transmission for incident radiation.

Abstract: A semiconductor structure is provided, and includes a first fin structure, a second fin structure, and a third fin structure over a substrate. The second fin structure is located between the first fin structure and the third fin structure. The semiconductor structure also includes a fin isolation structure formed between the first fin structure and the third fin structure; and a gate structure formed over the first fin structure, the second fin structure, the third fin structure and the fin isolation structure. The semiconductor structure further includes a plurality of epitaxial structures formed over the first fin structure, the second fin structure and the third fin structure. The semiconductor structure includes a dielectric material over the first epitaxial structure, the second epitaxial structure, and the third epitaxial structure; and a contact formed in the dielectric material and connected to the first epitaxial structure and the third epitaxial structure.

Abstract: A hinge device includes a fixed shaft, a rotating sleeve, a fixed connection member, a torsion spring, a rotating connection member and a friction resistance assembly. The rotating sleeve is rotatably mounted on the fixed shaft and is located between a fixed end and a free end. One end of the fixed connection member is fixedly connected to the free end, and the other end is provided with a first slot. Two ends of the torsion spring are respectively equipped with a first snap-in pin and a second snap-in pin. The first snap-in pin inserts into the first slot. An extension part protrudes from a fixed part of the of the rotating connection member and is provided with a second slot. The second snap-in pin inserts into the second slot. The friction resistance assembly is disposed on the fixed shaft to provide torsional resistance to the rotating sleeve.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern disposed within a first region from a top view perspective and extending along a first direction, a first phase shift circuit disposed within the first region, a first transmission circuit disposed within a second region from the top view perspective, and a first gate conductor extending from the first region to the second region along a second direction perpendicular to the first direction. The first phase shift circuit and the first transmission circuit are electrically connected with the first conductive pattern through the first gate conductor.

Abstract: A semiconductor device includes a semiconductor substrate, at least two source/drain features, at least two source/drain features, one or more channel layers, a gate structure, a first conductive feature, a second conductive feature, and an alignment mark. The semiconductor substrate has a first region and a second region next to the first region. The at least two source/drain features are disposed in the second region and are laterally arranged to each other. The one or more channel layers are disposed in the second region and connect the at least two source/drain features. The gate structure is disposed in the second region and engages the one or more channel layers and interposes the at least two source/drain features. The first conductive feature is disposed in the second region and is electrically coupled to the at least two source/drain features.

Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Abstract: A textile detection module is suitable for detecting a test specimen. The textile detection module includes a height sensor, an excitation light source, an optical detector, and a focuser. The height sensor is suitable for measuring a height of the test specimen to generate a height signal. The excitation light source provides an excitation light beam. The optical detector is disposed on a transmission path of the excitation light beam and is suitable for receiving the excitation light beam and emitting the excitation light beam along the optical axis and receiving a detection light beam to generate a detection result. The focuser is disposed on the transmission path of the excitation light beam emitted by the optical detector. The focuser includes a focus lens suitable for converting the excitation light beam into a focused excitation light beam.

Abstract: A control method for a multi-channel non-volatile memory is shown. When reading a read target on the non-volatile memory, the controller increases the read count of the monitored unit to which the read target belongs and, based on the read count, determines whether to move data of the monitored unit covering the read target to a safe space to deal with reading interference. The monitored unit is smaller than a cross-channel management unit in read-count group. The controller accesses a parallel accessing space of the non-volatile memory in parallel through all of the channels, and allocates the parallel accessing space based on the cross-channel management unit.

Abstract: An extraction device for a heating tracer includes a clamping assembly and a driving member. The clamping assembly includes a connecting seat, a first extrusion wheel and a second extrusion wheel rotatably arranged on the connecting seat. The first extrusion wheel and the second extrusion wheel are both an eccentric wheel. In use, the heating tracer is clamped between the first extrusion wheel and the second extrusion wheel, and is in contact with an outer circumference of the first extrusion wheel and the second extrusion wheel. The driving member includes a main body and a drive shaft arranged thereon. The main body is configured to drive the drive shaft to extend along an axial direction of the main body. The drive shaft is connected to an end of the connecting seat away from the first extrusion wheel and the second extrusion wheel.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a nanostructure, an isolation structure, an isolation fin, and a gate stack. The method includes turning the substrate upside down and removing the base to expose the isolation structure. The method includes partially removing the isolation structure to form a first trench in the isolation structure. The first trench exposes a portion of the isolation fin. The method includes removing the portion of the isolation fin through the first trench to form a second trench in the gate stack. The method includes partially removing the gate stack through the first trench and the second trench. The second trench passes through the gate stack and divides the gate stack into a first part and a second part.

Abstract: A surgical robot and a surgical robot system is disclosed. The surgical robot comprises a first robot arm, a second robot arm connected to the end of the first robot arm and used for mounting and controlling the motion posture of a surgical instrument, and a controller that controls the motion of the axes of the first robot arm and the second robot arm, wherein the end of the first robot arm is provided with a linear guide portion for the second robot arm to move linearly; and the first robot arm is connected to the end of the linear guide portion that is close to the second robot arm and used for mounting an end of the surgical instrument.

Abstract: In a flip chip package, lines, an identification line and a dummy line are provided on a first surface of a light-transmissive carrier, and a supportive layer is disposed on a second surface of the light-transmissive carrier. Bumps and an identification bump of a chip are bonded to the lines and the identification line, respectively. Shadows of the dummy line, the identification line and the identification bump which are projected on the second surface are visible from an opening of the supportive layer. The shadows can be inspected through the opening so as to know whether the bumps are bonded to the lines correctly.

Abstract: An MRAM structure includes an MTJ, a first SOT element, a conductive layer and a second SOT element disposed from bottom to top. A protective layer is disposed on the second SOT element. The protective layer covers and contacts a top surface of the second SOT element. The protective layer is an insulator. A conductive via penetrates the protective layer and contacts the second SOT element.

Abstract: A control method of a display panel and a display device are provided. In the method, at least one binding-point grayscale value is obtained at first; an initial-state control parameter, an initial-state brightness parameter, and a reference brightness parameter of a to-be-regulated region are determined according to each of the binding-point grayscale value; and a relative compensation brightness parameter of the binding-point grayscale value is determined according to the initial-state control parameter, the initial-state brightness parameter, and the reference brightness parameter of the binding-point grayscale value when a ratio of the initial-state brightness parameter to the reference brightness parameter is not within a preset range.

Abstract: A method of fabricating an MTJ device is provided including the following process. A first via is formed in the first dielectric layer. A first electrode layer is formed on the first dielectric layer and the first via. An MTJ stack layer is formed on the first electrode layer. A patterned second electrode layer is formed on the MTJ stack layer and used as a mask. A first ion beam etching process is performed to etch the patterned second electrode layer and pattern the MTJ stack layer and the first electrode layer to form a second electrode, an MTJ stack structure, and a first electrode. A first protective layer is formed to cover the second electrode and the MTJ stack structure. A second ion beam etching process is performed to remove a portion of the MTJ stack structure and a portion of the first electrode.