Abstract: A method includes bonding a first device die to a second device die through face-to-face bonding, wherein the second device die is in a device wafer, forming a gap-filling region to encircle the first device die, performing a backside-grinding process on the device wafer to reveal a through-via in the second device die, and forming a redistribution structure on the backside of the device wafer. The redistribution structure is electrically connected to the first device die through the through-via in the second device die. A supporting substrate is bonded to the first device die.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a metal rail, and a first source/drain contact and a second source/drain contact. The first transistor has a gate structure, a first source/drain feature, and a second source/drain feature. The first source/drain feature and the second source/drain feature are on opposite sides of the gate structure. The second transistor has the gate structure, a third source/drain feature directly over the first source/drain feature, and a fourth source/drain feature directly over the second source/drain feature. The metal rail extends in an X-direction and adjacent to the gate structure in a Y-direction. The first source/drain contact and the second source/drain contact each has an L-shape in a Y-Z cross-sectional view. The first source/drain contact electrically connects the first source/drain feature to the metal rail. The second source/drain contact electrically connects the fourth source/drain feature to the metal rail.

Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.

Abstract: A system includes one or more data processors configured to run a basic input/output system (BIOS) service and a bootloader configuration manager for tuning kernel parameters. The system further includes a non-transitory computer-readable storage medium containing instructions which, when executed on the one or more data processors, cause the one or more data processors to perform operations. The operations include receiving administrative inputs and checking the administrative inputs against a checklist to determine whether any errors are introduced by the administrative inputs. The operations further include writing the administrative inputs to a temporal configuration file in response to no errors being introduced by the administrative inputs. The operations further include exporting the temporal configuration file to a designated output path. The exported temporal configuration file includes kernel parameter settings for configuring a bootloader of a computing device.

Abstract: An automatic target image acquisition and calibration system for application in a defect inspection system is disclosed. During the defect inspection system working normally, the automatic target image acquisition and calibration system is configured to find a recognition structure from an article under inspection, and then determines a relative position and a relative 3D coordinate if the article. Therefore, a robotic arm is controlled to carry a camera to precisely face each of a plurality of inspected surfaces of the article, such that a plurality of article images are acquired by the camera. It is worth explaining that, during the defect inspection of the article, there is no need to modulate an image acquiring height and an image acquiring angle of the camera and an illumination of a light source.

Abstract: A semiconductor package having a fillet is provided. The semiconductor package includes a trace disposed within a solder mask that has a top surface. A first die is over the solder mask and mechanically couples with the trace. A first adhesive is between the trace and the first die where sides of the first die and the first adhesive define a die edge. The semiconductor package includes a fillet adjacent the die edge and a second die above the first die. The semiconductor package also includes a second adhesive having a bottom surface where the second adhesive is between the first die and the second die. The solder mask top surface, the first die surface, and the second adhesive bottom surface define a cavity where the fillet is within the cavity at the die edge.

Abstract: A method of forming a FinFET is disclosed. The method includes depositing a conductive material across each of a number of adjacent fins, depositing a sacrificial mask over the conductive material, patterning the conductive material with the sacrificial mask to form a plurality of conductive material segments, depositing a sacrificial layer over the sacrificial mask, and patterning the sacrificial layer, where a portion of the patterned sacrificial layer remains over the sacrificial mask, where a portion of the sacrificial mask is exposed, and where the exposed portion of the sacrificial mask extends across each of the adjacent fins. The method also includes removing the portion of the sacrificial layer over the sacrificial mask, after removing the portion of the sacrificial layer over the sacrificial mask, removing the sacrificial mask, epitaxially growing a plurality of source/drain regions from the semiconductor substrate, and electrically connecting the source/drain regions to other devices.

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.

Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.

Abstract: Disclosed herein is a probiotic composition that includes Lactobacillus salivarius subsp. salicinius AP-32, Lactobacillus johnsonii MH-68, and Bifidobacterium animalis subsp. lactis CP-9, which are deposited at the China Center for Type Culture Collection (CCTCC) respectively under accession numbers CCTCC M 2011127, CCTCC M 2011128, and CCTCC M 2014588. A number ratio of Lactobacillus salivarius subsp. salicinius AP-32, Lactobacillus johnsonii MH-68, and Bifidobacterium animalis subsp. lactis CP-9 ranges from 1:0.1:0.1 to 1:1:8. Also disclosed herein is use of the probiotic composition for alleviating type 1 diabetes mellitus (T1DM).

Abstract: A fixing device includes a circuit board, an insertion slot, and a fixing bracket. The circuit board has a peripheral recess, and the insertion slot is disposed on the circuit board. The fixing bracket is fixed in the peripheral recess, and the fixing bracket has a board, two lateral arms, and two guiding rails. The two lateral arms are connected to two corresponding sides of the board, and the two lateral arms are integrally formed from the board. In addition, the two guiding rails are respectively disposed at the two lateral arms, in which the two guiding rails extend towards the insertion slot.

Abstract: A transparent display panel with driving electrode regions, circuit wiring regions, and optically transparent regions is provided. The driving electrode regions are arranged into an array in a first direction and a second direction. An average light transmittance of the circuit wiring regions is less than ten percent, and an average light transmittance of the optically transparent regions is greater than that of the driving electrode regions and the circuit wiring regions. The first direction intersects the second direction. The circuit wiring regions connect the driving electrode regions at intervals, such that each optically transparent region spans among part of the driving electrode regions. The transparent display panel includes first signal lines and second signal lines extending along the circuit wiring regions, and each circuit wiring region is provided with at least one of the first signal lines and at least one of the second signal lines.

Abstract: A data migration method and an apparatus are provided. The method is as follows: sending, by a first storage system, a location update request to a location server, where the location update request is used to indicate the location server to update location information of a first bucket from being located in a second storage system to being located in the first storage system; migrating data in a first bucket from the second storage system; receiving a data access request, where the data access request is used to access the data in the first bucket; and determining based on a type of the data access request and a migration status of the data, that the first storage system or the second storage system processes the data access request.

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

Abstract: An abnormal traffic detection method is provided according to an embodiment of the disclosure. The method includes: obtaining network traffic data of a target device; sampling the network traffic data by a sampling window with a time length to obtain sampling data; generating, according to the sampling data, an image which presents a traffic feature of the network traffic data corresponding to the time length; and analyzing the image to generate evaluation information corresponding to an abnormal traffic. In addition, an abnormal traffic detection device is also provided according to an embodiment of the disclosure to improve a detection ability and/or an analysis ability for the abnormal traffic and/or a malware.

Abstract: A package includes a package component, a device die over and bonded to the package component, a metal cap having a top portion over the device die, and a thermal interface material between and contacting the device die and the metal cap. The thermal interface material includes a first portion directly over an inner portion of the device die, and a second portion extending directly over a corner region of the device die. The first portion has a first thickness. The second portion has a second thickness greater than the first thickness.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a source/drain region and a first conductive feature disposed below the source/drain region. The first conductive feature is electrically connected to the source/drain region. The structure further includes a second conductive feature disposed over the source/drain region, and the second conductive feature is electrically connected to the source/drain region. The structure further includes a third conductive feature disposed on and in contact with a first portion of the second conductive feature and a dielectric layer disposed on and in contact with a second portion of the second conductive feature.

Abstract: A multiport passive photonic light circuit chip has multiple waveguides written in at least two layers on a glass substrate. Some waveguides connect transmitting and receiving ports of an optical channel, some waveguides redirect a fraction of optical signals to some other receiving ports, and waveguides have circular cross-sectional shapes wherein a refractive index contrast is in the range of 0.2% to 2%.

Abstract: A semiconductor device is provided. The semiconductor device has a stack of parallel metal gates formed on a first side of a substrate, a first pair of insulation regions extending across the stack of parallel metal gates, a second pair of insulation regions replacing two of the parallel metal gates, a first isolated region enclosed by the first and second pairs of insulation layers, a first via formed within the isolated region, and an insulation layer replacing the metal gates located within the isolated region. Tree or more metal gates are located within the isolated region, and the first via extends through a portion of a center one of the three metal gates within the isolated region.

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.