SEMICONDUCTOR DEVICE AND ZENER DIODE HAVING BRANCH IMPURITY REGIONS
A semiconductor device includes a substrate, a well region of a first-conductivity type disposed in the substrate, a first impurity region of a second-conductivity type and having a plurality of branches disposed in the well region, a second impurity region of the first-conductivity type and having a plurality of branches, and a third impurity region of the first-conductivity type disposed in the well region. The second-conductivity type is opposite to the first-conductivity type. A portion of the first impurity region overlaps a portion of the third impurity region. The plurality of branches of the second impurity region are disposed in the third impurity region, and a portion of the third impurity region is disposed between the first impurity region and the second impurity region.
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Example embodiments relate to a semiconductor device and, more particularly, to a semiconductor device including a Zener diode having branch impurity regions.
BACKGROUNDIn general, a Zener diode operates with a reverse bias when it is applied in a circuit, When a reverse bias voltage applied to a Zener diode exceeds a certain value, the current flowing through the diode rises rapidly due to the electron tunneling effect, This reverse voltage is referred to as the Zener breakdown voltage. The current flow in the forward direction of a Zener diode is similar to that of a traditional diode.
The basic structure of a Zener diode includes a p-n junction. The Zener breakdown voltage can be adjusted by selecting an appropriate doping material and concentration. Conventional Zener diodes include doping areas that have the shape of a rectangle.
As shown in
According to a first aspect of the present disclosure, there is provided a semiconductor device. The semiconductor device includes a substrate, a well region of a first-conductivity type disposed in the substrate, a first impurity region of a second-conductivity type and having a plurality of branches disposed in the well region, a second impurity region of the first-conductivity type and having a plurality of branches, and a third impurity region of the first-conductivity type disposed in the well region. The second-conductivity type is opposite to the first-conductivity type. A portion of the first impurity region overlaps a portion of the third impurity region. The plurality of branches of the second impurity region is disposed in the third impurity region, and a portion of the third impurity region is disposed between the first impurity region and the second impurity region.
According to a second aspect of the present disclosure, there is provided a semiconductor device. The semiconductor device includes a substrate, a well region of a first-conductivity type disposed in the substrate, a first impurity region of a second-conductivity type, a second impurity region of the first-conductivity type, and a third impurity region of the first-conductivity type disposed in the well region. The first impurity region has a first branch extending in a first direction and a plurality of second branches extending in a second direction and connected to the first branch. The second impurity region has a third branch extending substantially in first direction and a plurality of fourth branches extending substantially in the second direction and connected with the third branch. The second-conductivity type is opposite to the first-conductivity type. A portion of the first impurity region overlaps a portion of the third impurity region. The second impurity region is disposed in the third impurity region, and a portion of the third impurity region is disposed between the first impurity region and the second impurity region.
According to a third aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device. The method includes forming a well region of the first-conductivity type in a substrate, forming a third impurity region of the first-conductivity type in the well region, forming a first impurity region of a second-conductivity type in the well region and having a plurality of branches, and forming a second impurity region of the first-conductivity type in the third impurity region and having a plurality of branches. The second-conductivity type is opposite to the first-conductivity type. A portion of the first impurity region is formed to overlap a portion of the third impurity region. A portion of the third impurity region is disposed between the first impurity region and the second impurity region.
Reference will now be made, by way of example, to the accompanying drawings which show example embodiments of the present application, and in which:
Hereinafter, embodiments consistent with the disclosure will be described with reference to the drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
Still referring to
In some embodiments, the first-conductivity type is n-type and the second-conductivity type is p-type, or vice versa. For example, in an n-type base Zener diode, well region 302 is n-type; first impurity region 306 is a p+ region having a doping concentration of 1018 to 1020 atoms/cm3; second impurity region 308 is an n+ region having a doping concentration of 1018 to 1020 atoms/cm3; and base region 310 is an n region having a doping concentration of 1016 to 1019 atoms/cm3, provided that second impurity region 308 has a higher doping concentration than that of base region 310. The doping concentration of base region 310 depends on a desired Zener breakdown voltage. More specifically, the doping concentrations of base (third impurity) region 310 and first impurity region 306 are tuning parameters to achieve a desired Zener breakdown voltage. The doping concentration of second impurity region 308 is greater than that of well region 302. In a p-type base Zener diode, well region 302 is p-type; first impurity region 306 is an n+ region having a doping concentration of 1018 to 1028 atoms/cm3; second impurity region 308 is a p+ region having a doping concentration of 1018 to 1020 atoms/cm3; and base region 310 is a p region having a doping concentration of 1016 to 1019 atoms/cm3. In some embodiments, the n-type dopant can be phosphorus or arsenic, and the p-type dopant can be boron.
Although branches 306a, 306b, 308a, 308b are shown in
The respective doping concentration ranges of the first, second, and third impurity regions of Zener diodes 600, 610, and 620 are substantially the same as described above for first, second, and third impurity regions of Zener diode 301, provided that the second impurity region has a higher doping concentration than that of the third impurity region.
Still referring to
In some embodiments, one or more of the steps shown in
The Zener diodes illustrated in this disclosure can be implemented in a voltage regulator, voltage shifter or waveform clipper, transient voltage suppressor, or any other circuit that uses a Zener diode.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
Claims
1. A semiconductor device comprising:
- a substrate;
- a well region of a first-conductivity type, disposed in the substrate;
- a first impurity region of a second-conductivity type, the first impurity region having a plurality of branches disposed in the well region, the second-conductivity type being opposite to the first-conductivity type;
- a second impurity region of the first-conductivity type, the second impurity region having a plurality of branches; and
- a third impurity region of the first-conductivity type disposed in the well region, a portion of the first impurity region overlapping a first portion of the third impurity region, the plurality of branches of the second impurity region being disposed in the third impurity region, and a second portion of the third impurity region being disposed between the first impurity region and the second impurity region.
2. The semiconductor device according to claim 1, wherein at least one portion of the plurality of branches of the first impurity region interlaces with at least one portion of the plurality of branches of the second impurity region.
3. The semiconductor device according to claim 1, wherein the plurality of branches of the first impurity region includes a first branch extending in a first direction and second branches extending from the first branch in a second direction different from the first direction.
4. The semiconductor device according to claim 3, wherein the plurality of branches of the first impurity region further includes third branches extending from the second branches in the first direction.
5. The semiconductor device according to claim 3, wherein the plurality of branches of the second impurity region includes a third branch extending in a third direction different from the second direction, free ends of the second branches being disposed toward the third branch.
6. The semiconductor device according to claim 5, wherein the plurality of branches of the second impurity region further includes fourth branches extending from the third branch in a fourth direction, free ends of the fourth branches being disposed toward the first branch.
7. The semiconductor device according to claim 6, wherein at least one of the second branches is disposed between a pair of the fourth branches, and at least one of the fourth branches is disposed between a pair of the second branches.
8. The semiconductor device according to claim 6, wherein the plurality of branches of the second impurity region further includes fifth branches extending from the fourth branches in the third direction.
9. The semiconductor device according to claim 5, wherein the free end of each of the second branches has a circular or polygonal shape.
10. The semiconductor device according to claim 1, further comprising:
- a dielectric layer disposed on the substrate;
- a first electrode coupled to the first impurity region via the dielectric layer; and
- a second electrode coupled to the second impurity region via the dielectric layer.
11. The semiconductor device according to claim 1, further comprising an isolation region disposed at a periphery of the third impurity region.
12. The semiconductor device according to claim 1, wherein the second impurity region has a doping concentration greater than a doping concentration of the third impurity region.
13. A semiconductor device comprising:
- a substrate;
- a well region of a first-conductivity type, disposed in the substrate;
- a first impurity region of a second-conductivity type, the first impurity region having a first branch extending in a first direction and a plurality of second branches extending in a second direction and connected to the first branch, the second-conductivity type being opposite to the first-conductivity type;
- a second impurity region of the first-conductivity type, the second impurity region having a third branch extending substantially in the first direction and a plurality of fourth branches extending substantially in the second direction and connected with the third branch; and
- a third impurity region of the first-conductivity type disposed in the well region, a portion of the first impurity region overlapping a first portion of the third impurity region, the second impurity region being disposed in the third impurity region, and a second portion of the third impurity region being disposed between the first impurity region and the second impurity region.
14. The semiconductor device according to claim 13, wherein at least one portion of the plurality of second branches of the first impurity region interlaces with at least one portion of the plurality of fourth branches of the second impurity region.
15. The semiconductor device according to claim 13, wherein free ends of the second branches are disposed toward the third branch.
16. The semiconductor device according to claim 13, wherein free ends of the fourth branches are disposed toward the first branch.
17. The semiconductor device according to claim 13, wherein at least one of the second branches is disposed between a pair of the fourth branches, and at least one of the fourth branches is disposed between a pair of the second branches.
18. A method for manufacturing a semiconductor device, comprising:
- forming a well region of the first-conductivity type in a substrate;
- forming a third impurity region of the first-conductivity type in the well region;
- forming a first impurity region of a second-conductivity type in the well region, the first impurity region having a plurality of branches, the second-conductivity type being opposite to the first-conductivity type, a portion of the first impurity region being formed to overlap a first portion of the third impurity region; and
- forming a second impurity region of the first-conductivity type in the third impurity region, the second impurity region having a plurality of branches, a second portion of the third impurity region being disposed between the first impurity region and the second impurity region.
Type: Application
Filed: Oct 14, 2015
Publication Date: Apr 20, 2017
Applicant:
Inventors: Yu-Jui CHANG (Hsinchu City), Cheng-Chi LIN (Toucheng Township)
Application Number: 14/882,997