Patents by Inventor Yu-Kai Lin

Yu-Kai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240243097
    Abstract: A power module package structure includes a first substrate and a power component. The first substrate includes at least one conductive layer on a surface thereof. The power component includes a first chip and a first spacer. The first chip has at least one electrode. The first spacer in a heat dissipation space between the first substrate and the first chip includes an insulating heat dissipation layer in the heat dissipation space and multiple vertical conductive connectors, each of the vertical conductive connectors penetrates the insulating heat dissipation layer. The insulating heat dissipation layer surrounds the vertical conductive connectors and electrically isolates the vertical conductive connectors. The vertical conductive connector includes two opposite ends, one end electrically connected to the conductive layer, and the other end electrically connected to the electrode to form a conductive path and a heat dissipation path between the first chip and the first substrate.
    Type: Application
    Filed: January 18, 2024
    Publication date: July 18, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Ming Peng, I-Hung Chiang, Chun-Kai Liu, Po-Kai Chiu, Hsin-Han Lin, Kuo-Shu Kao
  • Publication number: 20240170345
    Abstract: A method of manufacturing a circuit pattern structure, a measurement method, and a circuit pattern structure are provided. The method of manufacturing the circuit pattern structure includes: forming a dielectric layer; forming at least one first pad at least partially in the dielectric layer; forming a second pad adjacent to the at least one first pad and having a height greater than that of the at least one first pad.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 23, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Kai LIN, Chih-Cheng LEE
  • Patent number: 11972537
    Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: April 30, 2024
    Assignee: YU JUNG CHANG TECHNOLOGY CO., LTD.
    Inventors: Chih-Chuan Chen, Wei-Hsiang Tsai, Chin-Yu Chen, Ching-Cherng Sun, Jann-Long Chern, Yu-Kai Lin
  • Patent number: 11973039
    Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Hao Sung, Hsuan-Yu Chen, Yu-Kai Lin
  • Publication number: 20240118767
    Abstract: A touchpad has a substrate, a sensing panel and a cover stacked in a sequence. The sensing panel has multiple sensing traces formed thereon. At least one flexible connecting board is connected between the sensing panel and the substrate via its end. The connecting board has multiple extending traces formed thereon, which are thinner than the sensing traces, to form an electrical connection between the sensing traces and the controller on the substrate. The flexible connecting board is used to avoid the problem of trace breakage caused by direct bending of the end of the sensing panel, and the sensing traces are collected by extending traces with smaller line widths so as to reduce the width of the boundary area effectively.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 11, 2024
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventor: Yu-Kai LIN
  • Publication number: 20240079267
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Cheng SHIH, Tze-Liang LEE, Jen-Hung WANG, Yu-Kai LIN, Su-Jen SUNG
  • Patent number: 11848231
    Abstract: A method for forming a semiconductor device structure is provided. The method includes successively forming a first multi-layer etch stop structure and an insulating layer over a first conductive feature. The insulating layer and the first multi-layer etch stop structure are successively etched to form an opening substantially aligned to the first conductive feature. A second conductive feature is formed in the opening. The formation of the first multi-layer etch stop structure and the second multi-layer etch stop structure includes forming a first metal-containing dielectric layer, forming a silicon-containing dielectric layer over the first metal-containing dielectric layer, and forming a second metal-containing dielectric layer over the silicon-containing dielectric layer. The second metal-containing dielectric layer has a material that is different from the material of the first metal-containing dielectric layer.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Cheng Shih, Tze-Liang Lee, Jen-Hung Wang, Yu-Kai Lin, Su-Jen Sung
  • Publication number: 20230394269
    Abstract: A card having a fingerprint sensor and a manufacturing method of the same are provided. The fingerprint sensor is disposed between a substrate and a protection layer. The protection layer has a first area and a second area thereon. The roughness of the second area is smaller than the roughness of the first area. The second area corresponds to the sensing area of the fingerprint sensor. When the user's finger is wet, the second area may effectively keep the water from remaining on it. Thus, the water does not affect the effect of fingerprint sensing.
    Type: Application
    Filed: May 22, 2023
    Publication date: December 7, 2023
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: Yu-Kai LIN, Chien-Wen TSAI, Ta-Huang LIU
  • Publication number: 20230384176
    Abstract: A torque sensor includes a sleeve member configured to be mounted on a center shaft, and a tubular sensor body arranged coaxially with the sleeve member. At least one outer surface of the sleeve member includes one or more magnetostrictive elements. The tubular sensor body includes a bobbin for mounting a sensor coil. An induced current in the sensor coil is detected in response to pedaling by a user. The tubular sensor body includes one or more inclined surfaces inclined with respect to a radial direction of the torque sensor, the one or more inclined surfaces being coupled with the sleeve member or the center shaft.
    Type: Application
    Filed: May 24, 2022
    Publication date: November 30, 2023
    Applicant: GIANT MANUFACTURING CO., LTD.
    Inventors: Che-Wei HSU, Tzu-Yang HSIAO, Yu-Kai LIN
  • Patent number: 11769693
    Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: September 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Ping Tung, Yu-Kai Lin, Jen Hung Wang, Shing-Chyang Pan
  • Publication number: 20230274975
    Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 31, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Kai Lin, Su-Jen Sung, Tze-Liang Lee, Jen-Hung Wang
  • Publication number: 20230260832
    Abstract: Semiconductor devices and methods of manufacture are presented herein in which a etch stop layer is selectively deposited over a conductive contact. A dielectric layer is formed over the etch stop layer and an opening is formed through the dielectric layer and the etch stop layer to expose the conductive contact. Conductive material is then deposited to fill the opening.
    Type: Application
    Filed: June 3, 2022
    Publication date: August 17, 2023
    Inventors: Yu-Kai Lin, Po-Cheng Shih, Jr-Hung Li, Tze-Liang Lee
  • Patent number: 11670546
    Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Kai Lin, Su-Jen Sung, Tze-Liang Lee, Jen-Hung Wang
  • Publication number: 20230057550
    Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 23, 2023
    Inventors: Chih-Chuan CHEN, Wei-Hsiang TSAI, Chin-Yu CHEN, Ching-Cherng SUN, Jann-Long CHERN, Yu-Kai LIN
  • Publication number: 20220285210
    Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Kai Lin, Su-Jen Sung, Tze-Liang Lee, Jen-Hung Wang
  • Publication number: 20220208603
    Abstract: A method for forming a semiconductor device structure is provided. The method includes successively forming a first multi-layer etch stop structure and an insulating layer over a first conductive feature. The insulating layer and the first multi-layer etch stop structure are successively etched to form an opening substantially aligned to the first conductive feature. A second conductive feature is formed in the opening. The formation of the first multi-layer etch stop structure and the second multi-layer etch stop structure includes forming a first metal-containing dielectric layer, forming a silicon-containing dielectric layer over the first metal-containing dielectric layer, and forming a second metal-containing dielectric layer over the silicon-containing dielectric layer. The second metal-containing dielectric layer has a material that is different from the material of the first metal-containing dielectric layer.
    Type: Application
    Filed: March 16, 2022
    Publication date: June 30, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Cheng SHIH, Tze-Liang LEE, Jen-Hung WANG, Yu-Kai LIN, Su-Jen SUNG
  • Patent number: 11282742
    Abstract: A semiconductor device structure is provided. The structure includes a conductive feature formed in an insulating layer. The structure also includes a first metal-containing dielectric layer formed over the insulating layer and covering the top surface of the conductive feature. The structure further includes a silicon-containing dielectric layer formed over the first metal-containing dielectric layer. In addition, the structure includes a second metal-containing dielectric layer formed over the silicon-containing dielectric layer. The second metal-containing dielectric layer includes a material that is different than the material of the first metal-containing dielectric layer.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Cheng Shih, Tze-Liang Lee, Jen-Hung Wang, Yu-Kai Lin, Su-Jen Sung
  • Publication number: 20220058359
    Abstract: A fingerprint sensing module has a fingerprint sensor and a cover. The main color layer and the pattern layer are arranged between the cover and the fingerprint sensor. The pattern layer constitutes a predetermined pattern that is used to present the pattern of the button. The both sides of the main color layer are flush with both sides of the pattern layer, so that the capacitance variations in the corresponding pattern layer and the main color layer pass through the medium with the same thickness, and have an approximate capacitance variation mode. Thus, the sensed fingerprint image truly reflect the detected fingerprint image without being affected by the preset pattern, and a pattern layer with a certain thickness is used to enhance the color saturation presented by the predetermined pattern.
    Type: Application
    Filed: July 9, 2021
    Publication date: February 24, 2022
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventor: Yu-Kai LIN
  • Publication number: 20210288002
    Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Hao SUNG, Hsuan-Yu CHEN, Yu-Kai LIN
  • Publication number: 20210280460
    Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.
    Type: Application
    Filed: May 10, 2021
    Publication date: September 9, 2021
    Inventors: Szu-Ping Tung, Yu-Kai Lin, Jen Hung Wang, Shing-Chyang Pan