Patents by Inventor Yu-Kai Lin
Yu-Kai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143112Abstract: A touch sensing apparatus includes a panel with touch detection function and a touch detection circuitry. The touch detection circuitry is coupled to the panel, and is configured to detect a touch operation on the panel, record an error event of the touch sensing apparatus, and write the error event into an external storage medium via a data transmission interface thereof.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Inventors: Yu Nian OU, Chun Kai CHUANG, Pei-Yuan HUNG, Yung Hsiang LIN
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Patent number: 11972077Abstract: A resetting system includes a driver that controls a touchscreen, the driver including a driver communication interface that defines a bus for transferring a transfer signal; and an on-screen display (OSD) device that generates an OSD signal representing a predetermined reset image in response to a predetermined event, the OSD signal superimposing over pixels and graphics data to be rendered on the touchscreen; and a host that transfers the transfer signal to or from the driver, the host including a host communication interface that defines the bus for transferring the transfer signal to or from the driver.Type: GrantFiled: April 29, 2023Date of Patent: April 30, 2024Assignee: Himax Technologies LimitedInventors: Yu-Nian Ou, Chun-Kai Chuang, Pei-Yuan Hung, Yu-Hsiang Lin
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Publication number: 20240135043Abstract: An information handling system includes a printed circuit board, a screw, and a processor. The printed circuit board includes a through hole via. The through hole via includes top and bottom sections plated with a conductive plating material, and a middle section without any conductive plating material. The screw in physical communication with the top, middle, and bottom sections of the through hole via in the printed circuit board. The processor determines whether an electrical circuit is formed between the screw, the top section of the through hole via, and the bottom section of the through hole via. Based on the determination of the electrical circuit being formed, the processor provides an indication that no intrusion has been made into the information handling system.Type: ApplicationFiled: October 19, 2022Publication date: April 25, 2024Inventors: Yong-Teng Lin, Bradford Edward Vier, Chun-Kai Tzeng, Chin-Yao Hsu, Yu-Lin Tsai
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Publication number: 20240128127Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Kai Hsu, Ssu-l Fu, Chun-ya Chiu, Chi-Ting Wu, Chin-HUNG Chen, Yu-Hsiang Lin
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Publication number: 20240118767Abstract: A touchpad has a substrate, a sensing panel and a cover stacked in a sequence. The sensing panel has multiple sensing traces formed thereon. At least one flexible connecting board is connected between the sensing panel and the substrate via its end. The connecting board has multiple extending traces formed thereon, which are thinner than the sensing traces, to form an electrical connection between the sensing traces and the controller on the substrate. The flexible connecting board is used to avoid the problem of trace breakage caused by direct bending of the end of the sensing panel, and the sensing traces are collected by extending traces with smaller line widths so as to reduce the width of the boundary area effectively.Type: ApplicationFiled: September 28, 2023Publication date: April 11, 2024Applicant: ELAN MICROELECTRONICS CORPORATIONInventor: Yu-Kai LIN
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Publication number: 20240113187Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Jhu-Min Song, Ying-Chou Chen, Yi-Kai Ciou, Chien-Chih Chou, Fei-Yun Chen, Yu-Chang Jong, Chi-Te Lin
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Publication number: 20240111377Abstract: A touch detection circuitry includes an analog-to-digital converter (ADC), a controller, and a packet generator. The ADC is arranged to convert touch signals of a touch panel from analog form into digital form. The controller is electrically connected to the ADC, and is configured to calculate at least one coordinate point and at least one touch size respectively corresponding to at least one touch event on the touch panel based on the touch signals. The packet generator is electrically connected to the controller, and is configured to encapsulate the at least one coordinate point and the at least one touch size into a touch data packet.Type: ApplicationFiled: June 7, 2023Publication date: April 4, 2024Inventors: Yu Nian OU, Chun Kai CHUANG, Yu-Hsiang LIN, Chun-Lung TSAI
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Publication number: 20240079267Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Cheng SHIH, Tze-Liang LEE, Jen-Hung WANG, Yu-Kai LIN, Su-Jen SUNG
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Publication number: 20240071504Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Chun LIAO, Yu-Kai CHANG, Yi-Ching LIU, Yu-Ming LIN, Yih WANG, Chieh LEE
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Patent number: 11848231Abstract: A method for forming a semiconductor device structure is provided. The method includes successively forming a first multi-layer etch stop structure and an insulating layer over a first conductive feature. The insulating layer and the first multi-layer etch stop structure are successively etched to form an opening substantially aligned to the first conductive feature. A second conductive feature is formed in the opening. The formation of the first multi-layer etch stop structure and the second multi-layer etch stop structure includes forming a first metal-containing dielectric layer, forming a silicon-containing dielectric layer over the first metal-containing dielectric layer, and forming a second metal-containing dielectric layer over the silicon-containing dielectric layer. The second metal-containing dielectric layer has a material that is different from the material of the first metal-containing dielectric layer.Type: GrantFiled: March 16, 2022Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Cheng Shih, Tze-Liang Lee, Jen-Hung Wang, Yu-Kai Lin, Su-Jen Sung
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Publication number: 20230394269Abstract: A card having a fingerprint sensor and a manufacturing method of the same are provided. The fingerprint sensor is disposed between a substrate and a protection layer. The protection layer has a first area and a second area thereon. The roughness of the second area is smaller than the roughness of the first area. The second area corresponds to the sensing area of the fingerprint sensor. When the user's finger is wet, the second area may effectively keep the water from remaining on it. Thus, the water does not affect the effect of fingerprint sensing.Type: ApplicationFiled: May 22, 2023Publication date: December 7, 2023Applicant: ELAN MICROELECTRONICS CORPORATIONInventors: Yu-Kai LIN, Chien-Wen TSAI, Ta-Huang LIU
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Publication number: 20230384176Abstract: A torque sensor includes a sleeve member configured to be mounted on a center shaft, and a tubular sensor body arranged coaxially with the sleeve member. At least one outer surface of the sleeve member includes one or more magnetostrictive elements. The tubular sensor body includes a bobbin for mounting a sensor coil. An induced current in the sensor coil is detected in response to pedaling by a user. The tubular sensor body includes one or more inclined surfaces inclined with respect to a radial direction of the torque sensor, the one or more inclined surfaces being coupled with the sleeve member or the center shaft.Type: ApplicationFiled: May 24, 2022Publication date: November 30, 2023Applicant: GIANT MANUFACTURING CO., LTD.Inventors: Che-Wei HSU, Tzu-Yang HSIAO, Yu-Kai LIN
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Patent number: 11769693Abstract: A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.Type: GrantFiled: May 10, 2021Date of Patent: September 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Ping Tung, Yu-Kai Lin, Jen Hung Wang, Shing-Chyang Pan
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Publication number: 20230274975Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.Type: ApplicationFiled: May 1, 2023Publication date: August 31, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Kai Lin, Su-Jen Sung, Tze-Liang Lee, Jen-Hung Wang
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Publication number: 20230260832Abstract: Semiconductor devices and methods of manufacture are presented herein in which a etch stop layer is selectively deposited over a conductive contact. A dielectric layer is formed over the etch stop layer and an opening is formed through the dielectric layer and the etch stop layer to expose the conductive contact. Conductive material is then deposited to fill the opening.Type: ApplicationFiled: June 3, 2022Publication date: August 17, 2023Inventors: Yu-Kai Lin, Po-Cheng Shih, Jr-Hung Li, Tze-Liang Lee
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Patent number: 11670546Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.Type: GrantFiled: March 4, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Kai Lin, Su-Jen Sung, Tze-Liang Lee, Jen-Hung Wang
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Publication number: 20230057550Abstract: A method for flattening a three-dimensional shoe upper template is provided. The method includes providing a three-dimensional last model, obtaining a three-dimensional grid model, obtaining a three-dimensional thickened grid model, obtaining a two-dimensional initial-value grid model, and obtaining a two-dimensional grid model with the smallest energy value. A system and a non-transitory computer-readable medium for performing the method are also provided. The method makes it possible to precisely flatten a three-dimensional last model with a non-developable surface and thereby convert the three-dimensional last model into a two-dimensional grid model.Type: ApplicationFiled: August 19, 2022Publication date: February 23, 2023Inventors: Chih-Chuan CHEN, Wei-Hsiang TSAI, Chin-Yu CHEN, Ching-Cherng SUN, Jann-Long CHERN, Yu-Kai LIN
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Publication number: 20220285210Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.Type: ApplicationFiled: March 4, 2021Publication date: September 8, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Kai Lin, Su-Jen Sung, Tze-Liang Lee, Jen-Hung Wang
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Publication number: 20220208603Abstract: A method for forming a semiconductor device structure is provided. The method includes successively forming a first multi-layer etch stop structure and an insulating layer over a first conductive feature. The insulating layer and the first multi-layer etch stop structure are successively etched to form an opening substantially aligned to the first conductive feature. A second conductive feature is formed in the opening. The formation of the first multi-layer etch stop structure and the second multi-layer etch stop structure includes forming a first metal-containing dielectric layer, forming a silicon-containing dielectric layer over the first metal-containing dielectric layer, and forming a second metal-containing dielectric layer over the silicon-containing dielectric layer. The second metal-containing dielectric layer has a material that is different from the material of the first metal-containing dielectric layer.Type: ApplicationFiled: March 16, 2022Publication date: June 30, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Cheng SHIH, Tze-Liang LEE, Jen-Hung WANG, Yu-Kai LIN, Su-Jen SUNG
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Patent number: 11282742Abstract: A semiconductor device structure is provided. The structure includes a conductive feature formed in an insulating layer. The structure also includes a first metal-containing dielectric layer formed over the insulating layer and covering the top surface of the conductive feature. The structure further includes a silicon-containing dielectric layer formed over the first metal-containing dielectric layer. In addition, the structure includes a second metal-containing dielectric layer formed over the silicon-containing dielectric layer. The second metal-containing dielectric layer includes a material that is different than the material of the first metal-containing dielectric layer.Type: GrantFiled: October 17, 2019Date of Patent: March 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Cheng Shih, Tze-Liang Lee, Jen-Hung Wang, Yu-Kai Lin, Su-Jen Sung